A high-speed and low-complexity architecture for softmax function in deep learning

M Wang, S Lu, D Zhu, J Lin… - 2018 IEEE asia pacific …, 2018 - ieeexplore.ieee.org
Recently, significant improvement has been achieved for hardware architecture design of
deep neural networks (DNNs). However, the hardware implementation of one widely used …

[图书][B] Direct digital synthesizer

J Vankka, K Halonen, J Vankka, K Halonen - 2001 - Springer
2. Direct Digital Synthesizer 2.1 Conventional Direct Digital Synthesizer ~f = fC/k . 2J Page 1
2. Direct Digital Synthesizer In this chapter the operation of the direct digital synthesizer is first …

Efficient precision-adjustable architecture for softmax function in deep learning

D Zhu, S Lu, M Wang, J Lin… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
The softmax function has been widely used in deep neural networks (DNNs), and studies on
efficient hardware accelerators for DNN have also attracted tremendous attention. However …

[图书][B] Power management of digital circuits in deep sub-micron CMOS technologies

S Henzler - 2006 - books.google.com
In the deep sub-micron regime, the power consumption has become one of the most
important issues for competitive design of digital circuits. Due to dramatically increasing …

The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations

H Dawid, H Meyr - IEEE Transactions on Computers, 1996 - ieeexplore.ieee.org
The CORDIC algorithm is a well-known iterative method for the efficient computation of
vector rotations, and trigonometric and hyperbolic functions. Basically, CORDIC performs a …

[图书][B] Digital Signal processing for multimedia systems

KK Parhi, T Nishitami - 2018 - books.google.com
Addresses a wide selection of multimedia applications, programmable and custom
architectures for the implementations of multimedia systems, and arithmetic architectures …

On the design automation of the memory-based VLSI architectures for FIR filters

HR Lee, CW Jen, CM Liu - IEEE transactions on consumer …, 1993 - ieeexplore.ieee.org
An approach to automating the design of memory-based VLSI architectures for FIR (finite
impulse response) filters has been developed. The automation is based on the exploration …

Unified mixed radix 2-4 redundant CORDIC processor

E Antelo, JD Bruguera… - IEEE transactions on …, 1996 - ieeexplore.ieee.org
We present a unified mixed radix CORDIC algorithm with carry-save arithmetic with a
constant scale factor. The pipelined architecture of the processor is determined by a unique …

A new scalable VLSI architecture for Reed-Solomon decoders

W Wilhelm - IEEE Journal of Solid-State Circuits, 1999 - ieeexplore.ieee.org
A very-large-scale integration architecture for Reed-Solomon (RS) decoding is presented
that is scalable with respect to the throughput rate. This architecture enables given system …

A new hardware-efficient architecture for programmable FIR filters

HR Lee, CW Jen, CM Liu - … on Circuits and Systems II: Analog …, 1996 - ieeexplore.ieee.org
Although much research has been done on efficient high-speed filter architectures, much of
this work has focused on filters with fixed coefficients, such as Canonical Signed Digit …