Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described.
In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive …

(57) ABSTRACT A circuit can include a Voltage comparator V having a first input, a second
input, and an output; a first plurality of capacitors CI0: n) that each have a top plate and a …

Successive approximation register (SAR) and ramp analog to digital conversion (ADC)
methods, systems, and appara tus are disclosed. An analog voltage signal may be …

(57) ABSTRACT A method for evaluating capacitor weighting of an analog to-digital (ADC) is
provided. An equivalent weighting value of each composed capacitor in each sub-capacitor …

The present disclosure relates to a method for reducing power consumption, including:
connecting one terminal of each capacitor in a first and a second capacitor array of an SAR …

A circuit can include a voltage comparator V d having a first input, a second input, and an
output; a first plurality of capacitors C p [0: n] that each have a top plate and a bottom plate …

A configurable analog to digital converter (ADC) is provided. The configurable ADC includes
a comparator receiving and comparing a first analog voltage signal to a second analog …

(57) ABSTRACT A method for adaptively regulating a coding mode and a digital correction
circuit thereof are provided. The method is for a successive-approximation-register analog-to …

US9843340B2 - Semiconductor device - Google Patents US9843340B2 - Semiconductor device
- Google Patents Semiconductor device Download PDF Info Publication number US9843340B2 …

The invention includes a successive approximation register, a digital-to-analog converter, a
comparator and a control stage. The control stage initially sets the successive approximation …