The synchronous design paradigm dominates today's semiconductor industry. However, this
clocked approach is facing major challenges with today's high-speed, low-power design …

Validation is a critical component of any commercial design cycle. Testing-based
approaches have AQ1 been predominantly what has been used to ensure design …

NULL Convention Logic (NCL) circuits are asynchronous circuits and find application in SoC
design due to their delay-insensitive nature, which allows ease in resolution of timing issues …

Formal verification of asynchronous circuits is known to be challenging due to highly non-
deterministic behavior exhibited in these systems. One of the main challenges is that it is …

Self-timed circuits can be modeled in a link-joint style using a formally defined hardware
description language. It has previously been shown how functional properties of these …

Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive
(QDI) asynchronous design paradigm with enormous potential for industrial applications …

A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates
and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking …

This paper presents a methodology for formally verifying the functional correctness of self-
timed circuits whose data flows are free of feedback loops. In particular, we formalize the …

NULL convention logic and latency-insensitive circuits are delay-tolerant circuits that can be
synthesized from a synchronous speci cation. These design paradigms can use existing …

Abstract Pre-Charge Half Buffers (PCHB) and NULL convention Logic (NCL) are two major
commercially successful Quasi-Delay Insensitive (QDI) asynchronous paradigms, which are …