Respir: A response surface-based pareto iterative refinement for application-specific design space exploration

G Palermo, C Silvano, V Zaccaria - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Application-specific multiprocessor systems-on-chip (MPSoCs) are usually designed by
using a platform-based approach, where a wide range of customizable parameters can be …

Thermal and energy management of high-performance multicores: Distributed and self-calibrating model-predictive controller

A Bartolini, M Cacciari, A Tilli… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
As result of technology scaling, single-chip multicore power density increases and its spatial
and temporal workload variation leads to temperature hot-spots, which may cause …

Effective performance measurement and analysis of multithreaded applications

NR Tallent, JM Mellor-Crummey - … of the 14th ACM SIGPLAN symposium …, 2009 - dl.acm.org
Understanding why the performance of a multithreaded program does not improve linearly
with the number of cores in a shared-memory node populated with one or more multicore …

Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors

V Hanumaiah, S Vrudhula… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Extracting high performance from multi-core processors requires increased use of thermal
management techniques. In contrast to offline thermal management techniques, online …

CPM in CMPs: Coordinated power management in chip-multiprocessors

AK Mishra, S Srikantaiah, M Kandemir… - SC'10: Proceedings of …, 2010 - ieeexplore.ieee.org
Multiple clock domain architectures have recently been proposed to alleviate the power
problem in CMPs by having different frequency/voltage values assigned to each domain …

Composite-ISA cores: Enabling multi-ISA heterogeneity using a single ISA

A Venkat, H Basavaraj… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
Heterogeneous multicore architectures are comprised of multiple cores of different sizes,
organizations, and capabilities. These architectures maximize both performance and energy …

The garden of forking paths in visualization: A design space for reliable exploratory visual analytics: Position paper

X Pu, M Kay - 2018 ieee evaluation and beyond …, 2018 - ieeexplore.ieee.org
Turkey emphasized decades ago that taking exploratory findings as confirmatory is
“destructively foolish”. We reframe recent conversations about the reliability of results from …

Throughput optimal task allocation under thermal constraints for multi-core processors

V Hanumaiah, R Rao, S Vrudhula… - Proceedings of the 46th …, 2009 - dl.acm.org
It is known that temperature gradients and thermal hotspots affect the reliability of
microprocessors. Temperature is also an important constraint when maximizing the …

Distributed cooperative caching

E Herrero, J González, R Canal - … of the 17th international conference on …, 2008 - dl.acm.org
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient
scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration …

Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management

S Biswas, M Tiwari, T Sherwood… - Proceedings of the 38th …, 2011 - dl.acm.org
Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling
resources, especially in large-scale systems where cooling power can be 50~ 100% of IT …