Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units
J Battini, S Kosaraju - Silicon, 2023 - Springer
The design of a 20-FinFET novel full adder (NFA) with a new architecture employing Double
Gate-FinFETs is presented in this work. The feature of new topology is, the input carry of full …
Gate-FinFETs is presented in this work. The feature of new topology is, the input carry of full …
Low-power high-speed CNTFET-based 1-bit comparator design using CCT and STT techniques
Carbon Nanotube Field Effect Transistor (CNTFET) based VLSI circuits are now desired due
to low power and reduced chip area-which are in great demand in the VLSI realm. In this …
to low power and reduced chip area-which are in great demand in the VLSI realm. In this …
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units
This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology
J Battini, S Kosaraju - Semiconductor Science and Technology, 2024 - iopscience.iop.org
Conventional carry select adders (CCSA) have two stages and are followed by multiplexers.
CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry …
CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry …
FinFET-Premised 1-Bit Comparator Design Using CPTL and DCVSPG Techniques
For the efficient design of digital circuits many digital designing techniques have been
characterized by Pass Transistor Logic family. Pass transistor-based techniques prefer N …
characterized by Pass Transistor Logic family. Pass transistor-based techniques prefer N …
A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block
This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
A new 18nm FinFET-based Programmable Logic Array type Multiplexer for High-speed and Low-Power applications
The speed and power of a circuit are the primary attributes one looks for in a design. To
accompany a fast technologically driven world where usage of electronic devices is rapidly …
accompany a fast technologically driven world where usage of electronic devices is rapidly …
FinFET Based Low Power and High Speed 3-Stage Comparator
V Pavani, SS Kiran, T Yaswanth… - 2024 IEEE 16th …, 2024 - ieeexplore.ieee.org
This article presents a novel three-stage comparator design that effectively addresses
kickback noise, a major difficulty in comparator circuits, while achieving high speed and low …
kickback noise, a major difficulty in comparator circuits, while achieving high speed and low …