A structured review of sparse fast Fourier transform algorithms

E Rajaby, SM Sayedi - Digital Signal Processing, 2022 - Elsevier
Discrete Fourier transform (DFT) implementation requires high computational resources and
time; a computational complexity of order O (N 2) for a signal of size N. Fast Fourier …

FPT: A fixed-point accelerator for torus fully homomorphic encryption

M Van Beirendonck, JP D'Anvers, F Turan… - Proceedings of the …, 2023 - dl.acm.org
Fully Homomorphic Encryption (FHE) is a technique that allows computation on encrypted
data. It has the potential to drastically change privacy considerations in the cloud, but high …

The power of large language models for wireless communication system development: A case study on FPGA platforms

Y Du, H Deng, SC Liew, K Chen, Y Shao… - arXiv preprint arXiv …, 2023 - arxiv.org
Large language models (LLMs) have garnered significant attention across various research
disciplines, including the wireless communication community. There have been several …

Coarse-grained reconfigurable architectures for radio baseband processing: A survey

Z Hassan, A Ometov, ES Lohan, J Nurmi - Journal of Systems Architecture, 2024 - Elsevier
Emerging communication technologies, such as 5G and beyond, have introduced diverse
requirements that demand high performance and energy efficiency at all levels …

Strix: An end-to-end streaming architecture with two-level ciphertext batching for fully homomorphic encryption with programmable bootstrapping

A Putra, Prasetiyo, Y Chen, J Kim, JY Kim - … of the 56th Annual IEEE/ACM …, 2023 - dl.acm.org
Homomorphic encryption (HE) is a type of cryptography that allows computations to be
performed on encrypted data. The technique relies on learning with errors problem, where …

Energy-efficient fast Fourier transform for real-valued applications

C Eleftheriadis, G Karakonstantis - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This brief presents a new energy efficient Fast-Fourier Transform (FFT) architecture for real-
valued applications. The proposed architecture decimates the FFT in time domain with bit …

Serial butterflies for non-power-of-two FFT architectures in 5G and beyond

VM Bautista, M Garrido… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This paper presents new serial butterflies for non-power-of-two (NP2) fast Fourier transform
(FFT) architectures. The paper considers radices 2, 3, 4, and 5, which are used in FFTs for …

Bind the gap: Compiling real software to hardware FFT accelerators

J Woodruff, J Armengol-Estapé, S Ainsworth… - Proceedings of the 43rd …, 2022 - dl.acm.org
Specialized hardware accelerators continue to be a source of performance improvement.
However, such specialization comes at a programming price. The fundamental issue is that …

A 60-mode high-throughput parallel-processing FFT processor for 5G/4G applications

Y Guo, Z Wang, Q Hong, H Luo, X Qiu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article presents a 60-mode high-throughput parallel-processing memory-based fast
Fourier transform (FFT) processor for fifth-generation (5G)/4G applications. The proposed …

Memory-based FFT architecture with optimized number of multiplexers and memory usage

Z Kaya, M Garrido, J Takala - IEEE Transactions on Circuits and …, 2023 - ieeexplore.ieee.org
This brief presents a new-parallel radix-2 memory-based fast Fourier transform (FFT)
architecture. The aim of this brief is to reduce the number of multiplexers and achieve an …