A new parallel processor structure for Givens QR-decomposition intended for the FPGA
implementation is presented. The structure is derived using method of mapping regular …

A fault tolerant algorithm based on Givens rotations and a modified weighted checksum
method is proposed for the QR-decomposition of matrices. The algorithm enables us to …

In this paper, the fixed size processor array architecture, which is destined for realization of
LL T-decomposition of symmetrical positively definite matrices based on Cholesky algorithm …

In this paper, a method for the systematic generation of executing programs for processor
element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this …

AbstractIn the representation a new method for mapping DSP algorithms into MMX
architecture is considered. The method is based on the matrix-graph method for mapping …

In this paper, the problem of the designing of the processor array (PA) architectures for the
DSP problems solution is discussed on the example of the digital FIR-filtering algorithm. At …

1.2. Analysis of known fault tolerance methods and selecting of most suitable from them for
the designing of fault-tolerant VLSI parallel systems 1.3. Requirements to methods of the …

A technique for mapping irregular sparse matrix computations into regular parallel networks
is proposed. It is based on regularization of the original irregular graph of an algorithm. For …

The simple and feasible for CAD implementation method of deriving dependence graphs of
regular algorithms and several examples of pupposive graph transformations are …

In this paper, two fixed size processor array architectures, which are destined for realization
of several linear algebra algorithms, are proposed. In order to implementation of these …