This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock
is made possible with almost no penalty in phase noise performance thanks to the use of a …

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be
reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and …

A software-defined radio (SDR) should theoretically receive any modulated frequency
channel in the (un) licensed spectrum, and guarantee top performance with energy savings …

We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with
two-point modulation which was realized in 90-nm CMOS using only regular VT devices.; …

This paper presents the first published fully-integrated digital fractional-N PLL based on a
second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter …

This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock
generation in harsh environments like nuclear and space applications. The PLL has been …

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios,
which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter …

A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves
phase noise and spurious tone performance comparable to those of a high-performance …

This paper presents a wideband fractional-N synthesizer whose loop bandwidth is
controlled adaptively. A fast automatic frequency-control (AFC) technique which selects the …

Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable
frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is …