Low distortion 50 GSamples/s track-hold and sample-hold amplifiers

S Daneshgar, Z Griffith, M Seo… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
We report 50 GSamples/s track-hold amplifier (THA) and sample-hold amplifier (SHA)
designed and fabricated in a 250 nm InP double heterojunction bipolar transistor (DHBT) …

A 55-GHz-bandwidth track-and-hold amplifier in 28-nm low-power CMOS

G Tretter, D Fritsche, MM Khafaji… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-
power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a …

Design and analysis of CMOS high-speed high dynamic-range track-and-hold amplifiers

YC Liu, HY Chang, SY Huang… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are
presented in this paper using 65-and 90-nm CMOS processes. To achieve remarkable …

32-GS/s SiGe Track-and-Hold Amplifier with 58-GHz Bandwidth and− 64-dBc to− 29-dBc HD3

P Thomas, M Grözing, M Berroth - 2020 27th IEEE International …, 2020 - ieeexplore.ieee.org
We demonstrate an ultra-wideband 32-GS/s SiGe track-and-hold amplifier with 58-GHz
bandwidth and a compact footprint due to the inductorless design. The circuit achieves a …

70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

J Deza, A Ouslimani, A Konczykowska… - Electronics …, 2013 - Wiley Online Library
A differential 70 GSa/s track‐and‐hold amplifier has been designed and fabricated in a 320
GHz‐fT InP double heterojunction bipolar transistor process. Measurements show a 51 GHz …

0.8/2.2-GHz programmable active bandpass filters in InP/Si BiCMOS technology

Z Xu, D Winklea, TC Oh, S Kim… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Programmable active bandpass filters (BPFs) have been designed in a chip-scale
heterogeneous integration technology, which intimately integrates InP HBTs on a deep …

A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range

YC Liu, HY Chang, K Chen - 2014 IEEE MTT-S International …, 2014 - ieeexplore.ieee.org
A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The
cascode topology with inductive peaking technique is employed to enhance voltage …

A broadband DC-coupling 16 GS/s sample-and-hold amplifier in 0.13 μm SiGe BiCMOS process

H Ding, J Wang, X Cheng, D Wang - AEU-International Journal of …, 2019 - Elsevier
This paper presents a broadband DC-coupling master-slave sample-and-hold amplifier
(SHA) in 0.13 μm SiGe BiCMOS process. PMOS source follower is implemented as the input …

A 56-GS/s 8-Bit Time-Interleaved SAR ADC in 28-nm CMOS

K Sun - 2018 - scholar.smu.edu
Optical communication standards from 100 Gb/s to 200 Gb/s to 400 Gb/s generate the
growing demands on the performance of ADC than ever before. For example, the 400 Gb/s …

一款2 G/s 采样率20 GHz 带宽主从式跟踪保持电路设计研究

Z Guifu, Z Jie, L Youjiang - 强激光与粒子束, 2020 - hplpb.com.cn
设计了一款全差分, 20 GHz 带宽主从式跟踪保持芯片(MS-THA). 该芯片采样率为2 G/s,
工作带宽大于20 GHz, 采用0.13 μm SiGe BiCMOS 工艺实现. 该芯片采用传统的开关发射极 …