G Tretter, D Fritsche, MM Khafaji… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low- power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a …
YC Liu, HY Chang, SY Huang… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65-and 90-nm CMOS processes. To achieve remarkable …
We demonstrate an ultra-wideband 32-GS/s SiGe track-and-hold amplifier with 58-GHz bandwidth and a compact footprint due to the inductorless design. The circuit achieves a …
J Deza, A Ouslimani, A Konczykowska… - Electronics …, 2013 - Wiley Online Library
A differential 70 GSa/s track‐and‐hold amplifier has been designed and fabricated in a 320 GHz‐fT InP double heterojunction bipolar transistor process. Measurements show a 51 GHz …
Z Xu, D Winklea, TC Oh, S Kim… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Programmable active bandpass filters (BPFs) have been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep …
YC Liu, HY Chang, K Chen - 2014 IEEE MTT-S International …, 2014 - ieeexplore.ieee.org
A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage …
H Ding, J Wang, X Cheng, D Wang - AEU-International Journal of …, 2019 - Elsevier
This paper presents a broadband DC-coupling master-slave sample-and-hold amplifier (SHA) in 0.13 μm SiGe BiCMOS process. PMOS source follower is implemented as the input …
Optical communication standards from 100 Gb/s to 200 Gb/s to 400 Gb/s generate the growing demands on the performance of ADC than ever before. For example, the 400 Gb/s …