With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-
the-field faults. To be broadly deployable, the hardware reliability solution must incur low …

The sustained push toward smaller and smaller technology sizes has reached a point where
device reliability has moved to the forefront of concerns for next-generation designs. Silicon …

As silicon process technology scales deeper into the nanometer regime, hardware defects
are becoming more common. Such defects are bound to hinder the correct operation of …

Extreme scaling practices in silicon technology are quickly leading to integrated circuit
components with limited reliability, where phenomena such as early-transistor failures, gate …

Dynamic test compaction procedures use independent fault sets to guide the generation of
compact test sets. In addition, a maximal independent fault set provides a lower bound on …

With test quality being an imperative, this paper presents a methodology on how to apply
volume scan diagnosis-known from the field of yield learning-to the domain of test quality …

It is reported that many cell-internal defects remain undetected when VLSI testing is
performed using test sets generated for only traditional fault models like stuck-at faults and …

This work proposes a new, software-based, defect detection and diagnosis technique. We
introduce a novel set of instructions, called access-control extensions (ACE), that can access …

This paper presents a scan architecture-California scan-that achieves high quality and low
power testing by modifying test patterns in the test application process. The architecture is …

In this paper, we will present two different applications of “test pattern sampling” for logic
testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The …