The miniaturization of electronics has been an important topic of study for several decades.
The established roadmaps following Moore's Law have encountered bottlenecks in recent …

This review investigates the measurement methods employed to assess the geometry and
electrical properties of through-silicon vias (TSVs) and examines the reliability issues …

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …

Three-dimensional (3D) integration has emerged as a potential solution to the wiring limits
imposed on chip performance, power dissipation, and packaging form factor beyond the 14 …

Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of
3D integration. This paper presents a numerical modeling of TSV filling concerning the …

In this study, copper filling in through-silicon via (TSV) by pulse periodic reverse
electroplating and low alpha solder bumping on Cu-filled TSVs was investigated. The via …

Copper (Cu) electroplating is a mature technology, and has been extensively applied in
microelectronic industry. With the development of advanced microelectronic packaging, Cu …

An electrically functional freestanding Si interposer for 3-D heterogeneous integration
applications is designed and successfully fabricated. The interposer employs multilevel …

Since voids and seams are easily formed during the process of filling TSVs with high aspect
ratio, good methods that can achieve the superfilling of TSVs are eagerly needed. This …

Cu-wire overhang bonding process is investigated first by a high-speed camera system. It
was found that the greater impact, rebound, and deflection of overhang die during the Cu …