A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino
resolves the tradeoff between performance and reliability in conventional CD-domino logic …

Several design techniques for high-performance and power-efficient CMOS comparators are
proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the …

With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip
(SoC) has become an essential technique to reduce product cost. With this progress and …

The high switching activity of wide fan-in dynamic domino gates introduces significant power
overhead that poses a limitation on using these compact high-speed circuits. This paper …

We present a design methodology for synchronous single-rail domino logic circuits, where
inverting and nonmonotonic logic functions can be integrated into a pipeline with almost …

Data-driven dynamic logic (D 3 L) uses local data instead of a global clock to maintain
correct precharge and evaluation phases. Eliminating the clock from dynamic gates yields …

Intricacy and performance estimation of VLSI IC's escalates as the device dimension goes
minuscule, but the performance of IC's has been improved exponentially over the years …

Scaling and power reduction trends in future technologies will cause subthreshold leakage
currents to become an increasingly large component of total power dissipation. As a result …

Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates,
which increases the power consumption and slows down the evaluation. We propose a four …

In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to
high switching activity at the dynamic and the output nodes introducing a significant power …