Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

S Nemati, M Haghi Kashani… - IET Circuits, Devices & …, 2023 - Wiley Online Library
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …

Design of energy-efficient and robust ternary circuits for nanotechnology

MH Moaiyeri, A Doostaregan, K Navi - IET Circuits, Devices & Systems, 2011 - IET
Novel high-performance ternary circuits for nanotechnology are presented here. Each of
these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the …

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

MH Moaiyeri, RF Mirzaee… - IET Computers & …, 2013 - Wiley Online Library
This study presents new low‐power multiple‐valued logic (MVL) circuits for nanoelectronics.
These carbon nanotube field effect transistor (FET)(CNTFET)‐based MVL circuits are …

Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing

E Faghih, MR Taheri, K Navi, N Bagherzadeh - … Computing: Informatics and …, 2023 - Elsevier
Nowadays, quantum computing plays a significant role in reducing the execution time in
complicated computations. There are different reversible algorithms for quantum …

Estimation Of Reliability Of D Flip-Flops Using Mc Analysis

K Ismail, N Khalil - Journal of VLSI Circuits And Systems, 2019 - vlsijournal.com
As the day by day size of the electronic devices has been decreased by scaling down the of
the VLSI technology. For any electronic devices reliability is one of the best performance …

All-optical symmetric ternary logic gate

T Chattopadhyay - Optics & Laser Technology, 2010 - Elsevier
Symmetric ternary number (radix= 3) has three logical states (1¯, 0, 1). It is very much useful
in carry free arithmetical operation. Beside this, the logical operation using this type of …

On the design of new low-power CMOS standard ternary logic gates

A Doostaregan, MH Moaiyeri, K Navi… - 2010 15th CSI …, 2010 - ieeexplore.ieee.org
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS
technology is proposed in this paper. This inverter could be used as a fundamental block for …

Efficient exploration of on-chip bus architectures and memory allocation

S Kim, C Im, S Ha - Proceedings of the 2nd IEEE/ACM/IFIP international …, 2004 - dl.acm.org
Separation between computation and communication in system design allows the system
designer to explore the communication architecture independently of component selection …

Exploring Ternary Computing: Design of a Superscalar CPU and Carry-Lookahead Adder

OC Moholth - 2024 - openarchive.usn.no
This thesis explores the design and architecture of a balanced ternary RISC-V-like Energy
efficient Balanced tErnary Logic (REBEL)-2 Central Processing Unit (CPU). There is a …

[PDF][PDF] Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device

H Gundersen - Oslo: Oslo University, 2008 - researchgate.net
Mostly all electronics used in computers today are based on binary logic. However, does the
binary logic have the capacity to be the leading technology in the future? Thus I raise the …