Memristor-based hardware accelerator for image compression

Y Halawani, B Mohammad, M Al-Qutayri… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
Memristor-based hardware accelerators are gaining an increased attention as a potential
candidate to speed-up the vector-matrix operations commonly needed in many digital image …

Low-power VLSI architectures for DCT\/DWT: precision vs approximation for HD video, biomedical, and smart antenna applications

A Madanayake, RJ Cintra, V Dimitrov… - IEEE Circuits and …, 2015 - ieeexplore.ieee.org
The DCT and the DWT are used in a number of emerging DSP applications, such as, HD
video compression, biomedical imaging, and smart antenna beamformers for wireless …

SMFrWF: Segmented modified fractional wavelet filter: Fast low-memory discrete wavelet transform (DWT)

M Tausif, E Khan, M Hasan, M Reisslein - IEEE Access, 2019 - ieeexplore.ieee.org
This paper proposes a novel algorithm to compute the 2-D discrete wavelet transform (DWT)
of high-resolution (HR) images on low-cost visual sensor and Internet of Things (IoT) nodes …

A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT

Y Hu, CC Jong - IEEE Transactions on signal processing, 2013 - ieeexplore.ieee.org
In this paper, we present a novel memory-efficient high-throughput scalable architecture for
multi-level 2-D DWT. We studied the existing DWT architectures and observed that data …

A memory-efficient scalable architecture for lifting-based discrete wavelet transform

Y Hu, CC Jong - IEEE Transactions on Circuits and Systems II …, 2013 - ieeexplore.ieee.org
In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory
efficiency and short critical path. The memory efficiency is achieved with a novel scanning …

Hardware-efficient DWT architecture for image processing in visual sensors networks

A George - IEEE Sensors Journal, 2023 - ieeexplore.ieee.org
This article proposes a fractional wavelet filter (FrWF)-based 2-D discrete wavelet transform
(DWT) architecture for the 9/7 Cohen–Daubechies–Feauveau (CDF) filter employed at the …

VLSI architectures for the 4-tap and 6-tap 2-D Daubechies wavelet filters using algebraic integers

SK Madishetty, A Madanayake… - … on Circuits and …, 2012 - ieeexplore.ieee.org
This paper proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4
and-6 2-D wavelet filters having error-free integer-based computation. Digital VLSI …

Low memory architectures of fractional wavelet filter for low-cost visual sensors and wearable devices

M Tausif, A Jain, E Khan, M Hasan - IEEE Sensors Journal, 2019 - ieeexplore.ieee.org
This paper proposes a low memory architecture of fractional wavelet filter for computing two-
dimensional discrete wavelet transform of gray-scale images. The proposed architecture …

Low-cost lifting architecture and lossless implementation of Daubechies-8 wavelets

MM Hasan, KA Wahid - … Transactions on Circuits and Systems I …, 2018 - ieeexplore.ieee.org
This paper presents three lifting structures of Daubechies-8 (also known as D8) wavelet
transform using efficient factorization of the polyphase matrix. All new filter coefficients are …

Multiplier‐less pipeline architecture for lifting‐based two‐dimensional discrete wavelet transform

A Darji, SN Merchant… - IET Computers & Digital …, 2015 - Wiley Online Library
In this study, the authors present a multiplier‐less, high‐speed and low‐power pipeline
architecture with novel dual Z‐scanning technique for lifting‐based two‐dimensional (2D) …