Integrated circuit (IC) technology has grown tremendously over the last few decades. The
prime goal has been to achieve low-power and high-performance in logic and memory …

A physically based compact analytical single electron transistor (SET) model is proposed for
hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the" …

In this work, we propose a compact, physically based, analytical single-electron transistor
(SET) model suitable for the design and analysis of realistic SET circuits. The model is …

Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which
resistance and capacitance parameters of source/drain junctions are not equal, has been …

This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A
comprehensive review of modeling techniques and previous models was carried out aiming …

A novel quasi-analytical model for single electron transistors (SETS) is proposed and
validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and …

As the nanotechnology rose to the surface, single electron transistor (SET) was invented. In
contrast to the well-known response of MOS current, SET current has peaks at certain gate …

Multiple-valued logic (MVL) decreases interconnection requirement and power consumption
by realizing more data transmission over an interconnection wire. This paper investigates …

We examine the performance of custom circuits in an emerging technology known as three-
dimensional integration. By combining multiple device layers with a high-density inter-layer …

In this paper, CMOS evolution and their fundamental and practical limitations are briefly
reviewed, and the working principles, performance, and fabrication of single-electron …