Cheshire: A lightweight, linux-capable risc-v host platform for domain-specific accelerator plug-in

A Ottaviano, T Benz, P Scheffler… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Power and cost constraints in the Internet-of-Things (IoT) extreme-edge and TinyML
domains, coupled with increasing performance requirements, motivate a trend toward …

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

S Di Girolamo, A Kurth, A Calotoiu… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
The capacity of offloading data and control tasks to the network is becoming increasingly
important, especially if we consider the faster growth of network speed when compared to …

Cohmeleon: Learning-based orchestration of accelerator coherence in heterogeneous SoCs

J Zuckerman, D Giri, J Kwon, P Mantovani… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
One of the most critical aspects of integrating loosely-coupled accelerators in
heterogeneous SoC architectures is orchestrating their interactions with the memory …

{OSMOSIS}: Enabling {Multi-Tenancy} in Datacenter {SmartNICs}

M Khalilov, M Chrapek, S Shen, A Vezzu… - 2024 USENIX Annual …, 2024 - usenix.org
Multi-tenancy is essential for unleashing SmartNIC's potential in datacenters. Our systematic
analysis in this work shows that existing on-path SmartNICs have resource multiplexing …

Agiler: An adaptive heterogeneous tile-based many-core architecture for risc-v processors

A Kamaleldin, D Göhringer - IEEE Access, 2022 - ieeexplore.ieee.org
Tile-based many-core architectures are extensively used in modern system-on-chip designs
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …

Sparse Hamming Graph: A Customizable Network-on-Chip Topology

P Iff, M Besta, M Cavalcante, T Fischer… - 2023 60th ACM/IEEE …, 2023 - ieeexplore.ieee.org
Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs).
Customization of the NoC topology is necessary to reach the diverse design goals of …

A Highly-Scalable Deep-Learning Accelerator With a Cost-Effective Chip-to-Chip Adapter and a C2C-Communication-Aware Scheduler

J Kim, C Park, E Hyun, XT Nguyen… - IEEE Journal on …, 2024 - ieeexplore.ieee.org
Multi-chip-module (MCM) technology heralds a new era for scalable DNN inference
systems, offering a cost-effective alternative to large-scale monolithic designs by lowering …

Herov2: Full-stack open-source research platform for heterogeneous computing

A Kurth, B Forsberg, L Benini - IEEE Transactions on Parallel …, 2022 - ieeexplore.ieee.org
Heterogeneous computers integrate general-purpose host processors with domain-specific
accelerators to combine versatility with efficiency and high performance. To realize the full …

Banshee: A fast LLVM-based RISC-V binary translator

S Riedel, F Schuiki, P Scheffler… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
System simulators are essential for the exploration, evaluation, and verification of manycore
processors and are vital for writing software and developing programming models in …

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support

T Fischer, M Rogenmoser, T Benz… - arXiv preprint arXiv …, 2024 - arxiv.org
The new generation of domain-specific AI accelerators is characterized by rapidly increasing
demands for bulk data transfers, as opposed to small, latency-critical cache line transfers …