STT-BNN: A novel STT-MRAM in-memory computing macro for binary neural networks

TN Pham, QK Trinh, IJ Chang… - IEEE Journal on …, 2022 - ieeexplore.ieee.org
This paper presents a novel architecture for in-memory computation of binary neural network
(BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are …

STT-BSNN: An in-memory deep binary spiking neural network based on STT-MRAM

VT Nguyen, QK Trinh, R Zhang, Y Nakashima - IEEE Access, 2021 - ieeexplore.ieee.org
This paper proposes an in-memory binary spiking neural network (BSNN) based on spin-
transfer-torque magnetoresistive RAM (STT-MRAM). We propose residual BSNN learning …

NUTS-BSNN: A non-uniform time-step binarized spiking neural network with energy-efficient in-memory computing macro

VN Dinh, NM Bui, VT Nguyen, D John, LY Lin, QK Trinh - Neurocomputing, 2023 - Elsevier
This work introduces a network architecture NUTS-BSNN: A Non-uniform Time-step
Binarized Spiking Neural Network. NUTS-BSNN is a fully binarized spiking neural network …

High-Performance STT-MRAM-Based Computing-in-Memory Scheme Utilizing Data Read Feature

B Wu, K Liu, T Yu, H Zhu, K Chen, C Yan… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
With the development of Artificial Intelligence (AI) and Binary neural networks (BNN), the
computing efficiency of the computing system is expected to be much better, however …

[HTML][HTML] Probability distribution of write failure in a memory cell array consisting of magnetic tunnel junction elements with distributed write error rates

H Arai, T Hirofuchi, H Imamura - AIP Advances, 2024 - pubs.aip.org
Write failure (WF) is a major reliability issue for applications of magnetoresistive random
access memory (MRAM), and much effort has been devoted to reducing the write error rate …

XNOR-BSNN: In-Memory Computing Model for Deep Binarized Spiking Neural Network

VT Nguyen, QK Trinh, R Zhang… - … Conference on High …, 2021 - ieeexplore.ieee.org
This paper proposes a residual binarized spiking neural network (B-SNN) model suited for
in-memory computing (IMC) implementation. While in most of the prior arts, due to the nature …

Characteristic time of transition from write error to retention error in voltage-controlled magnetoresistive random-access memory

H Arai, H Imamura - Journal of Magnetism and Magnetic Materials, 2023 - Elsevier
Voltage controlled magnetoresistive random access memory (VC MRAM) is a promising
candidate for a future low-power high-density memory. The main causes of bit errors in VC …

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory

R Zhou, B Liu, X Si, H Cai - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
Computing-in-memory (CIM) based on spin transfer torque magnetic random access
memory (STT-MRAM) is promised to be an effective way to overcome the" memory wall" …

Energy Efficient DSHE based Analogue Multiply Accumulate Computing Crossbar Architecture

S Soni, G Verma, AK Shukla… - 2023 IEEE Asia Pacific …, 2023 - ieeexplore.ieee.org
The implementation of non-volatile memories (NVMs) based in-memory computing (IMC)
have a great potential for neural network applications. Both digital and analog based IMC …