Hybrid-SBST methodology for efficient testing of processor cores

N Kranitis, A Merentitis, G Theodorou… - IEEE Design & Test …, 2008 - ieeexplore.ieee.org
In this article, we introduce a hybrid-SBST methodology for efficient testing of commercial
processor cores that effectively uses the advantages of various SBST methodologies. Self …

Automatic test program generation using executing-trace-based constraint extraction for embedded processors

Y Zhang, H Li, X Li - IEEE Transactions on Very Large Scale …, 2012 - ieeexplore.ieee.org
Software-based self-testing (SBST) has been a promising method for processor testing, but
the complexity of the state-of-art processors still poses great challenges for SBST. This …

Software-based self-testing with multiple-level abstractions for soft processor cores

CH Chen, CK Wei, TH Lu… - IEEE transactions on very …, 2007 - ieeexplore.ieee.org
Software-based self-test (SBST) is a promising approach for testing a processor core
embedded in a system-on-chip (SoC) system. Test routine development for SBST can be …

A methodology for detecting performance faults in microprocessors via performance monitoring hardware

M Hatzimihail, M Psarakis… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
Speculative execution of instructions boosts performance in modern microprocessors.
Control and data flow dependencies are overcome through speculation mechanisms, such …

Design of a step-up/step-down k (= 2, 3,...)-fibonacci dc-dc converter designed by switched-capacitor techniques

K Eguchi, S Hirata, M Shimoji… - 2012 Fifth International …, 2012 - ieeexplore.ieee.org
A step-up/step-down k (= 2, 3,...)-Fibonacci switched-capacitor (SC) DC-DC converter is
proposed in this paper. Unlike conventional Fibonacci step-up converter, the proposed …

Low energy online self-test of embedded processors in dependable WSN nodes

A Merentitis, N Kranitis, A Paschalis… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Wireless Sensor Network (WSN) nodes are often deployed in harsh environments where the
possibility of permanent and especially intermittent faults due to environmental hazards is …

Directed random SBST generation for on-line testing of pipelined processors

A Merentitis, G Theodorou… - 2008 14th IEEE …, 2008 - ieeexplore.ieee.org
Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-
line testing of processors integrated in embedded system applications. It offers the potential …

On-Chip Structures for Fmax Binning and Optimization

D Zhang, Q Ren, D Su - Sensors, 2022 - mdpi.com
Process variations during manufacturing lead to differences in the performance of the chips.
In order to better utilize the performance of the chips, it is necessary to perform maximum …

An on-chip binning sensor for low-cost and accurate speed binning

D Zhang, X Wang - 2017 2nd IEEE International Conference on …, 2017 - ieeexplore.ieee.org
Due to process variations at the very low technology nodes, the manufactured chips are
grouped into different speed bins. Currently, various types of maximum operation frequency …

Simulation-based functional test justification using a boolean data miner

CHP Wen, O Guzey, LC Wang… - … Conference on Computer …, 2006 - ieeexplore.ieee.org
In simulation-based functional verification, composing and debugging testbenches can be
tedious and time-consuming. A simulation data-mining approach, called TTPG (C. Wen, LC …