High-throughput and low-latency reconfigurable routing topology for fast ai mpsoc architecture

P Bhulania, M R. Tripathy, A Khan - Applications of Artificial Intelligence …, 2021 - Springer
Multiprocessor system-on-chip (MPSoC) widely uses in various applications due to its
capacity of delivering the aggressive performances in the low power cost. The System-on …

High-performance dynamic elastic pipelines

H Rezaei, SA Moghaddam, A Rahmati - Microprocessors and …, 2018 - Elsevier
In this paper, we will propose a new class of synchronous elastic pipelines called Dynamic
Elastic Pipeline (DELP) that employs dynamic logic family and achieves improved …

Design of a variable precision CORDIC coprocessor for RISC-V architecture based on FinFET process

B Zhao, M Yin, W Zhang, H Liu, Z Li - IEICE Electronics Express, 2023 - jstage.jst.go.jp
This paper proposes a 32-bit RISC-V microprocessor for the IoT, which consists of the
Hummingbird e203 and a configurable precision CO-ordinate Rotation Digital Computer …

High-performance asynchronous pipeline using embedded delay element

RK Kavitha, A Khajamastan, YR Akhilesh… - Microprocessors and …, 2020 - Elsevier
In this paper, a novel N-bit single-rail pipeline denoted as Embedded Delay Pipeline (EDP)
is proposed. It consists of N-Embedded Delay Elements (EDEs) which act both as control …

Novel Asynchronous Pipeline Architectures for High-Throughput Applications

K Sravani, R Rao - Arabian Journal for Science and Engineering, 2020 - Springer
This paper introduces two novel high-throughput asynchronous pipeline methods, suitable
for gate-level pipelined systems. The proposed methods, named as early acknowledged …

Interface cerveau-machine: de nouvelles perspectives grâce à l'accélération matérielle

E Libessart - 2018 - theses.hal.science
Les interfaces cerveau-machine (ICM) permettent de contrôler un appareil électronique
grâce aux signaux cérébraux. Plusieurs méthodes de mesure de ces signaux, invasives ou …

Routing Method for Interplanetary Satellite Communication in IoT Networks Based on IPv6

P Dobrowolski, G Debita, P Falkowski-Gilski - Data Intelligence and …, 2022 - Springer
The matter of interplanetary network (IPN) connection is a complex and sophisticated topic.
Space missions are aimed inter alia at studying the outer planets of our solar system. Data …

Design and implementation of extended 16 bit co-operative arithmetic and logic unit (CALU) for 16 bit instructions

TM Dudhane, T Ravi - Journal of Low Power Electronics, 2019 - ingentaconnect.com
CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit,
CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined …

Efficient closely-coupled integration of AES coprocessor with LEON3 processor

R Bansal, A Karmakar - International Symposium on VLSI Design and Test, 2019 - Springer
This paper proposes an efficient closely-coupled method for integrating the widely used
Advanced Encryption Standard (AES) hardware as a coprocessor IP core in the LEON3 …

PRESENT crypto-core as closely-coupled coprocessor for efficient embedded socs

R Bansal - 2020 24th International Symposium on VLSI Design …, 2020 - ieeexplore.ieee.org
PRESENT cipher is a lightweight block cipher best suited for securing low-cost hardware
having single-chip solutions or SoCs for enhanced system-level efficiency. This paper …