During the past decades, an incredible change of technology has been observed in many
devices: traditionally used mechanical parts have often been first replaced by analog …

Dedicated point-to-point wires (DW) can be used in place of a Packet-Switched Networks-on-
a-Chip (PSNoC) for fast linking of separately-compiled FPGA blocks, providing higher …

Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues,
by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with …

The theory of latency-insensitive design (LID) was recently invented to cope with the time
closure problem in otherwise synchronous circuits and programs. The idea is to allow the …

Du fait de la miniaturisation grandissante des circuits électroniques, la conception de
système sur puce actuelle, se heurte au problème des latences sur les fils d'interconnexions …

Latency-insensitive (LI) systems are those which can function correctly in spite of delays
along its connecting wires. This delay is assumed to be a multiple of the clock period. The …

Synchronous models are used to specify embedded systems functions in a clear and
unambiguous way and allow verification of properties using formal methods. The …

Cette thèse présente de nouveaux résultats liant la théorie des systèmes dits insensibles à
la latence, à une sous-classe des réseaux de Pétri dénommée Marked Event Graph et son …

Cette thèse définit un nouveau modèle de calcul et de communication, dénommé graphe à
routage k-périodique (KRG). Ce modèle, de la famille des réseaux de processus flots de …

System-on-chip designs are composed of modules working at different clock frequencies.
These modules will communicate using control and data events. However, they cannot be …