Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors

T Koizumi, R Shioya, S Sugita, T Amano… - Proceedings of the 56th …, 2023 - dl.acm.org
Out-of-order superscalar processors are currently the only architecture that speeds up
irregular programs, but they suffer from poor power efficiency. To tackle this issue, we …

Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue

K Mori, S Kosugi, H Yoshida… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
There is a high demand to reduce the energy consumption of microprocessors. Among
resources in a processor, the issue queue is one of the largest energy consumers, with …

[PDF][PDF] 处理器值预测技术研究

黄立波, 杨凌, 杨乾明, 马胜, 王永文, 隋兵才, 沈立… - 电子学报, 2023 - ejournal.org.cn
当今的处理器性能与存储器带宽和延迟严重失衡的问题限制了计算系统的整体性能,
而存储器的性能对制程工艺不敏感, 在后摩尔时代下很难再通过集成电路制造工艺的迭代获得 …

Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues

D Chen, T Zhang, Y Huang, J Zhu, Y Liu… - Proceedings of the 50th …, 2023 - dl.acm.org
Modern out-of-order processors call for more aggressive scheduling techniques such as
priority scheduling and out-of-order commit to make use of increasing core resources. Since …

Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows

Y Lee, J Lee, J Kwon, Y Lee, WW Ro - … of the 61st ACM/IEEE Design …, 2024 - dl.acm.org
Modern out-of-order microprocessors are increasingly expanding resources such as reorder
buffer (ROB) and instruction queue (IQ) for memory-level parallelism (MLP). While this …

ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension

M Kimura, R Shioya - Proceedings of the 29th ACM/IEEE International …, 2024 - dl.acm.org
Vector instructions have recently been introduced in general-purpose CPUs. These general-
purpose CPUs typically employ out-of-order superscalar processors to execute scalar …