The VPR toolset has been widely used in FPGA architecture and CAD research, but has not
evolved over the past decade. This article describes and illustrates the use of a new version …

In this work, we present Odin II, a framework for Verilog Hardware Description Language
(HDL) synthesis that allows researchers to investigate approaches/improvements to different …

Abstract Design automation or computer-aided design (CAD) for field programmable gate
arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA …

Ensuring proper privacy and protection of the information stored, communicated, processed,
and disseminated in the cloud as well as of the users accessing such an information is one …

Neural networks are considered as promising candidates for implementing functions in
memristor crossbar array with high tolerance to device defects and variations. Based on …

Dynamically reconfigurable hardware combines hardware performance with software-like
flexibility and finds increasing use in networked systems. The capability to load hardware …

Embodiments relate to a method and computer program for determining a placement of at
least one circuit for a reconfigurable logic device. The method comprises obtaining (110) …

This article proposes Proof-carrying Hardware (PCH) as a novel approach to bring formal
verification to hardware security for reconfigurable platforms. The Proof-carrying Hardware …

FPGA technology mapping is the process of implementing a hardware design expressed in
high-level HDL (hardware design language) code using the low-level, architecture-specific …

The addition of FPGAs in the cloud is an emerging effort to support acceleration and
performance with the flexibility of logic reprogramming. The underlying logic per unit area of …