Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition

CD English, G Shine, VE Dorgan, KC Saraswat… - Nano …, 2016 - ACS Publications
The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact
resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts …

Healing of donor defect states in monolayer molybdenum disulfide using oxygen-incorporated chemical vapour deposition

PC Shen, Y Lin, C Su, C McGahan, AY Lu, X Ji… - Nature …, 2022 - nature.com
Two-dimensional molybdenum disulfide (MoS2) is a semiconductor that could be used to
build scaled transistors and other advanced electronic and optoelectronic devices. However …

[HTML][HTML] Comprehensive Review of FinFET Technology: History, Structure, Challenges, Innovations, and Emerging Sensing Applications

K Karimi, A Fardoost, M Javanmard - Micromachines, 2024 - mdpi.com
The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological
advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk …

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

HH Radamson, M Kolahdouz - Journal of Materials Science: Materials in …, 2015 - Springer
This article reviews the selective epitaxy growth of intrinsic, B-and C-doped SiGe layers on
recessed (or flat) exposed Si areas for MOSFETs as well as on Si-fins for FinFETs. A …

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T Chiarella, L Witters, A Mercha, C Kerner… - Solid-State …, 2010 - Elsevier
The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks
to its improved electrostatics and short-channel effect control. FinFETs represent one of the …

Effect of Mole fraction and Fin Material on Performance Parameter of 14 nm Heterojunction Si1-xGex FinFET and Application as an Inverter

S Verma, SL Tripathi - Silicon, 2022 - Springer
This work presents a new SOI 14 nm heterojunction FinFET with Si 1-x Ge x fin for low-
power digital logic circuits. The channel region of the proposed device consists of Si 1-x Ge …

Multi-gate devices for the 32 nm technology node and beyond

N Collaert, A De Keersgieter, A Dixit, I Ferain… - Solid-State …, 2008 - Elsevier
Due to the limited control of the short channel effects, the high junction leakage caused by
band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling …

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width

R Coquand, S Barraud, M Cassé, P Leroux… - Solid-State …, 2013 - Elsevier
In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an
alternative way to planar devices for the future CMOS technological nodes (14 nm and …

Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?

AB Sachid, R Francis, MS Baghini… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T FIN)
necessary to maintain acceptable short-channel performance. For the 45 nm technology …

Impact & Analysis of Inverted-T shaped Fin on the Performance parameters of 14-nm heterojunction FinFET

S Verma, SL Tripathi - Silicon, 2022 - Springer
A new high-performance inverted-T shaped 14 nm heterojunction FinFETs has been
proposed that originate from the rectangular fin structures. The rationale for proposing this …