Advanced quad flat no lead chip package having a cavity structure and manufacturing methods thereof

PHC Chien, PC Hu, CW Chen… - US Patent App. 12/192,702, 2009 - Google Patents
In one innovative aspect, the invention relates to a semiconductor package. In one
embodiment, the semicon ductor package includes a die pad, a plurality of leads, a …

Advanced quad flat non-leaded package structure and manufacturing method thereof

PHC Chien, PC Hu, PS Chiang, WL Cheng - US Patent 8,237,250, 2012 - Google Patents
The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality
of wires, and a molding compound. The carrier includes a die pad and a plurality of leads …

Semiconductor device and semiconductor module

R Yoneyama, H Okabe, N Nishida, T Obara - US Patent 9,613,888, 2017 - Google Patents
A semiconductor device in the preferred embodiment includes: a lead frame comprising a
die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface …

Lead frame and semiconductor device

S Hayashi - US Patent 9,831,158, 2017 - Google Patents
A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead
frame; and an encapsulation resin, wherein a convexo-concave portion including a plurality …

Semiconductor device and production method thereof

S Mizusaki, K Fukuhara - US Patent 8,373,258, 2013 - Google Patents
BACKGROUND The present invention relates to a semiconductor device and a production
method thereof; in particular a technology effective when it is applied to a semiconductor …

Rounded die configuration for stress minimization and enhanced thermo-mechanical reliability

LT Nguyen, V Gumaste - US Patent App. 11/959,422, 2009 - Google Patents
One aspect of the invention pertains to a semiconductor die with rounded sidewall junction
edge corners. Such rounding reduces stress accumulations at those corners. In other …

Very extremely thin semiconductor package

S Nondhasitthichai, S Sirinorakul - US Patent 8,575,762, 2013 - Google Patents
(57) ABSTRACT A package and method of making thereof. The package includes a? rst
plated area, a second plated area, a die, a bond, and a molding. The die is attached to the …

Semiconductor package having a cavity structure

PHC Chien, PC Hu, CW Chen, HY Lee - US Patent 8,492,883, 2013 - Google Patents
A semiconductor package and related methods are described. In one embodiment, the
package includes a die pad, a plural ity of leads, a chip, and a package body. The die pad …

Wire bond mold lock method and structure

LM Higgins III - US Patent 9,685,351, 2017 - Google Patents
(57) ABSTRACT A method and apparatus are described for fabricating a microchip structure
(70) which protects interior electrical integrated circuits and components (120) attached to a …

Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof

Y Lee, S Kim - US Patent App. 12/683,426, 2011 - Google Patents
A package structure and related methods are described. In one embodiment, the package
structure includes a chip, a plurality of leads disposed around and electrically coupled to the …