Comparative analysis of yield optimized pulsed flip-flops
In this paper, the influence of random process variations on pulsed flip-flops is analyzed.
Monte Carlo simulation results demonstrate that using transistor reordering and dual …
Monte Carlo simulation results demonstrate that using transistor reordering and dual …
Timing reliability improvement of master-slave flip-flops in the presence of aging effects
Manufacturing process variations and transistor's aging effects are two major concerns for
reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of …
reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of …
The Hidden Behavior of a D-Latch
J Maier, A Steininger, R Najvirt - IEEE Transactions on Circuits …, 2023 - ieeexplore.ieee.org
For clock and data transitions in close temporal proximity, synchronous memory elements
potentially enter metastability, which leads to unintended output behavior. Although …
potentially enter metastability, which leads to unintended output behavior. Although …
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation
S Nishizawa, T Ishihara… - 2014 27th IEEE …, 2014 - ieeexplore.ieee.org
This paper describes the process variation tolerant design of DFFs for low voltage operation.
Within-die random variation have a strong impact on the delay performance of DFF …
Within-die random variation have a strong impact on the delay performance of DFF …
[PDF][PDF] 集積回路のエネルギー効率向上を目指した性能ばらつきの予測技術とセルライブラリの構築に関する研究
西澤真一 - 2015 - repository.kulib.kyoto-u.ac.jp
(論文内容の要旨) 本研究は, 集積回路のエネルギー効率向上を図るための重要技術として,
回路遅延の高精度な見積りを可能とするためのトランジスタ特性ばらつきと供給電圧ばらつきの …
回路遅延の高精度な見積りを可能とするためのトランジスタ特性ばらつきと供給電圧ばらつきの …