[图书][B] CMOS electronics: how it works, how it fails

J Segura, CF Hawkins - 2004 - books.google.com
CMOS manufacturing environments are surrounded with symptoms that can indicate serious
test, design, or reliability problems, which, in turn, can affect the financial as well as the …

Iddq testing for CMOS VLSI

R Rajsuman - Proceedings of the IEEE, 2000 - ieeexplore.ieee.org
It is little more than 15-years since the idea of Iddq testing was first proposed. Many
semiconductor companies now consider Iddq testing as an integral part of the overall testing …

Test method evaluation experiments and data

P Nigh, A Gattiker - … Test Conference 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
Understanding the effectiveness of their production tests is a critical task for IC suppliers.
Numerous trends suggesting that conventionally applied test methods must change to meet …

Current signatures [VLSI circuit testing]

AE Gattiker, W Maly - Proceedings of 14th VLSI Test …, 1996 - ieeexplore.ieee.org
In this paper we demonstrate that performing I/sub DDQ/testing against a single threshold
current value does not make sense. In place of the single current threshold we propose the" …

Current signatures: application

AE Gattiker, W Maly - Proceedings International Test …, 1997 - ieeexplore.ieee.org
Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of
applicability. The new concept of the current signature may expand this limit under the …

The behavior and testing implications of CMOS IC logic gate open circuits

CL Henderson, JM Soden, CF Hawkins - 1991 - osti.gov
The electrical and test properties of several logic gate open circuit defect structures were
measured. Results indicate that tunneling current across fine geometry discontinuities …

Microfluidic MEMS for semiconductor processing

AK Henning, JS Fitch, JM Harris… - … Technology: Part B, 1998 - ieeexplore.ieee.org
The advent of MEMS (microelectromechanical systems) will enable dramatic changes in
semiconductor processing. MEMS-based devices offer opportunities to achieve higher …

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/testing

VH Champac, A Rubio… - IEEE Transactions on …, 1994 - ieeexplore.ieee.org
The behavior of an MOS transistor with an open in the polygate path (floating transistor gate
defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/is …

[图书][B] Introduction to IDDQ testing

S Chakravarty, PJ Thadikaran - 2012 - books.google.com
Testing techniques for VLSI circuits are undergoing many exciting changes. The
predominant method for testing digital circuits consists of applying a set of input stimuli to the …

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

ST Su, RZ Makki, T Nagle - Journal of Electronic Testing, 1995 - Springer
We present a new method for testing digital CMOS integrated circuits. The new method is
based on the following premise: monitor the switching behavior of a circuit as opposed to the …