When mismatches are present in a dynamic comparator, due to internal positive feedback
and transient response, it is always challenging to analytically predict the input-referred …

The circuit performance of dynamic CMOS comparators has been reviewed in this work.
CMOS dynamic comparators contributes a major role on the implementation of mixed signal …

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D)
converter that can sample input frequencies above 200 MHz. The converter utilizes a front …

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive
divider, differential pair, and charge distribution comparators, are analyzed. The topologies …

A new pseudo asynchronous level crossing analogue-to-digital converter (ADC) architecture
targeted for low-power, implantable, long-term biomedical sensing applications is …

This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low
offset voltage compared to the traditional dynamic comparators. This paper comprises a …

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter
(ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient …

This paper presents a 10-bits successive approximation register analog-to-digital converter
(SAR ADC) for low-power applications. The input signals are multiplied by two because the …

This brief presents the architectural concept of an optimal subranging ADC, obtained with
the cascade of a Flash and a SAR, which is also explored through its practical design and …

A new low offset dynamic comparator for high resolution high speed analog-to-digital
application has been designed. Inputs are reconfigured from the typical differential pair …