In one embodiment, a network device includes ports to serve as ingress ports and as egress
ports, streaming aggregation circuitry to analyze received data packets to identify the data …

A computing unit is disclosed, comprising a first memory bank for storing input activations
and a second memory bank for storing parameters used in performing computations. The …

Some embodiments provide a method for compiling a neural network (NN) program for an
NN inference circuit (NNIC) that includes multiple partial dot product computation cir cuits …

Systems for neural network computation are provided. A neural network processor
comprises a plurality of neural cores. The neural network processor has one or more pro …

Some embodiments provide a neural network inference circuit (NNIC) for executing a NN
that includes multiple computation nodes at multiple layers. Each of a set of the computation …

Part of the communications includes collective operation such as (by way of non-limiting
example) doing sum of multiple vectors (element-wise add operation) from multiple …

a typical way for an integrated circuit to compute these weight values is to use multiply-
accumulate (MAC) circuits that repeatedly perform the multiplication of an input value by a …

A method in which a plurality of process are configured to hold a block of data destined for
other processes, with data repacking circuitry including receiving circuitry configured to …

(57) ABSTRACT A network element includes a plurality of ports, multiple computational
modules, configurable forwarding circuitry and a central block. The ports include child ports …

Described herein is a neural network accelerator with a set of neural processing units and
an instruction set for execu tion on the neural processing units. The instruction set is a …