[PDF][PDF] Formal verification of embedded logic controller specification with computer deduction in temporal logic

I Grobelna - Przeglad Elektrotechniczny, 2011 - researchgate.net
Embedded logic controllers specification is the first step in development process. Possible
errors in this phase [1] may influence oncoming phases or even the whole venture. Usually …

[HTML][HTML] Comparing model checkers for timed UML activity diagrams

Z Daw, R Cleaveland - Science of Computer Programming, 2015 - Elsevier
This paper describes the results of an experimental study on the use of model checkers to
verify properties of UML activity diagrams. The motivation for the study derives from the …

Model checking of UML activity diagrams in logic controllers design

I Grobelna, M Grobelny, M Adamski - … -RELCOMEX. June 30–July 4, 2014 …, 2014 - Springer
The article presents a novel approach to model checking of UML activity diagrams (in
version 2. x) for logic controller specification. A novel idea to design embedded systems by …

Performances evaluation and Petri nets

O Diallo, JJPC Rodrigues, M Sene - Modeling and Simulation of Computer …, 2015 - Elsevier
Petri nets have become a tremendously important mathematical and graphical tool in
modeling and performance evaluation of real systems with discrete events that are …

Hardware behavioural modelling, verification and synthesis with UML 2. x activity diagrams

M Grobelny, I Grobelna, M Adamski - IFAC Proceedings Volumes, 2012 - Elsevier
Modelling of hardware behavior is the fundamental process of hardware design project.
Possible specification techniques, like UML 2. x Activity Diagrams or Control Interpreted …

Model checking of control interpreted Petri nets

I Grobelna, M Adamski - Proceedings of the 18th International …, 2011 - ieeexplore.ieee.org
The paper presents an original approach to model checking of Control Interpreted Petri
Nets. Petri Nets are currently used in the industry, but they are mostly verified only for …

Petri net models of discrete logics used in control algorithms developed in ladder diagram language

JC Quezada, E Flores, E Baños, V Quezada - The International Journal of …, 2023 - Springer
Control algorithms for programmable logic controllers are still developed based on the
experience of those responsible for control in the industry. The IEC-61131-3 standard …

Simulation and validation of diagram ladder—petri nets

JC Quezada, J Medina, E Flores, JC Seck Tuoh… - … International Journal of …, 2017 - Springer
Automated systems based on programmable logic controllers (PLC) are still applied in
discrete event systems (DES) for controlling and monitoring of industrial processes signals …

[PDF][PDF] Formalizing ladder logic programs and timing charts for fault impact analysis and verification of fault tolerance

A Ebnenasir - Michigan Technological University, CS-TR-23-01, 2023 - mtu.edu
This paper presents a novel approach for modeling, automated analysis and verification of
fault tolerance in Ladder Logic (LL) programs for Programmable Logic Controllers (PLCs) …

Software framework for the development of context-aware reconfigurable systems

S Fkaier - 2021 - publikationen.sulb.uni-saarland.de
In this project we propose a new software framework for the development of context-aware
and secure controlling software of distributed reconfigurable systems. Context-awareness is …