A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

F Klass, C Amir, A Das, K Aingaran… - IEEE Journal of Solid …, 1999 - ieeexplore.ieee.org
In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has
been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that …

MOUSETRAP: High-speed transition-signaling asynchronous pipelines

M Singh, SM Nowick - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
An asynchronous pipeline style is introduced for high-speed applications, called
MOUSETRAP. The pipeline uses standard transparent latches and static logic in its …

MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines

M Singh, SM Nowick - Proceedings 2001 IEEE International …, 2001 - ieeexplore.ieee.org
A new asynchronous pipeline design is introduced for high-speed applications. The pipeline
uses simple transparent latches in its datapath, and small latch controllers consisting of only …

The design of high-performance dynamic asynchronous pipelines: Lookahead style

M Singh, SM Nowick - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which
use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are …

Asynchronous pipeline with latch controllers

M Singh, SM Nowick - US Patent 6,958,627, 2005 - Google Patents
An asynchronous pipeline for high-Speed applications uses Simple transparent latches in its
datapath and Small latch controllers for each pipeline Stage. The Stages communicate with …

The design of high-performance dynamic asynchronous pipelines: High-capacity style

M Singh, SM Nowick - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
This paper introduces a high-throughput asynchronous pipeline style, called high-capacity
(HC) pipelines, targeted to datapaths that use dynamic logic. This approach includes a novel …

The test of time. Clock-cycle estimation and test challenges for future microprocessors

PD Fisher, R Nesbitt - IEEE Circuits and Devices Magazine, 1998 - ieeexplore.ieee.org
Even with aggressive new technology, the complex high-performance processor will require
special design techniques and architectures to take advantage of new interconnect and …

Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic OR gates

H Mostafa, M Anis, M Elmasry - IEEE Transactions on Circuits …, 2011 - ieeexplore.ieee.org
Dynamic gates are preferred in the design of high-performance modules in modern
microprocessors due to the relatively high speed of dynamic gates compared with that of …

Relative timing based verification of timed circuits and systems

H Kim, PA Beerel, K Stevens - Proceedings Eighth International …, 2002 - ieeexplore.ieee.org
Aggressive timed circuits, including synchronous and asynchronous self-resetting circuits,
are particularly challenging to design and verify due to complicated timing constraints that …

Dynamic circuit techniques in deep submicron technologies: Domino logic reconsidered

C Cornelius, S Koppe… - 2006 IEEE International …, 2006 - ieeexplore.ieee.org
Dynamic circuit techniques offer potential advantages over static CMOS. Domino circuits are
the most widespread representative in high performance designs but suffer increasingly …