A hybrid selection strategy based on traffic analysis for improving performance in networks on chip

M Trik, AMNG Molk, F Ghasemi… - Journal of …, 2022 - Wiley Online Library
Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have
been able to handle the communication between processing cores, inspired by computer …

Evaluation of the routing algorithms for NoC-based MPSoC: a fuzzy multi-criteria decision-making approach

YR Muhsen, NA Husin, MB Zolkepli, N Manshor… - IEEE …, 2023 - ieeexplore.ieee.org
Routing algorithms play a crucial role in the performance of Network-on-Chip (NoC)-based
Multi-Processor Systems-on-Chip (MPSoC). However, the selection of appropriate and …

Runtime detection of a bandwidth denial attack from a rogue network-on-chip

R JS, DM Ancajas, K Chakraborty, S Roy - Proceedings of the 9th …, 2015 - dl.acm.org
In this paper, we propose a covert threat model for MPSoCs designed using 3rd party
Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on …

CATRA-congestion aware trapezoid-based routing algorithm for on-chip networks

M Ebrahimi, M Daneshtalab, P Liljeberg… - … , Automation & Test …, 2012 - ieeexplore.ieee.org
Congestion occurs frequently in Networks-on-Chip when the packets demands exceed the
capacity of network resources. Congestion-aware routing algorithms can greatly improve the …

Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead

J Liu, J Harkin, Y Li, LP Maguire - IEEE transactions on …, 2015 - ieeexplore.ieee.org
Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC)
due to the increase in physical defects in advanced manufacturing processes. Two novel …

Low cost fault-tolerant routing algorithm for networks-on-chip

J Liu, J Harkin, Y Li, L Maguire - Microprocessors and Microsystems, 2015 - Elsevier
A novel adaptive routing algorithm–Efficient Dynamic Adaptive Routing (EDAR) is proposed
to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path …

Review of network on chip routing algorithms

K Ahmad, M Sethi - EAI Endorsed Transactions on Context-aware Systems …, 2020 - eudl.eu
Abstract System on chip (SoC) is an integrated circuit in which components are
communicating through the bus interconnection system. Network on chip (NoC) is a …

High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET-based adaptive monitoring platform

AM Rahmani, KR Vaddina, K Latif… - IEEE Transactions …, 2012 - ieeexplore.ieee.org
The emerging three-dimensional integrated circuits (3D-ICs) achieve greater device
integration and enhanced system performance at lower cost and reduced area footprint …

Near-ideal networks-on-chip for servers

P Lotfi-Kamran, M Modarressi… - … Symposium on High …, 2017 - ieeexplore.ieee.org
Server workloads benefit from execution on many-core processors due to their massive
request-level parallelism. A key characteristic of server workloads is the large instruction …

Congestion‐Aware Routing Algorithm for NoC Using Data Packets

K Ahmad, MAJ Sethi, R Ullah, I Ahmed… - Wireless …, 2021 - Wiley Online Library
Network on Chip (NoC) is a communication framework for the Multiprocessor System on
Chip (MPSoC). It is a router‐based communication system. In NoC architecture, nodes of …