From interpreted Petri net specification to reprogrammable logic controller design
M Adamski, JL Monteiro - ISIE'2000. Proceedings of the 2000 …, 2000 - ieeexplore.ieee.org
The goal of this paper is to present the design methodology for the modelling and synthesis
of discrete event controllers for compact, fast and reliable embedded systems, using related …
of discrete event controllers for compact, fast and reliable embedded systems, using related …
Synthesis of Petri nets into FPGA with operation flexible memories
A Bukowiec, M Adamski - 2012 IEEE 15th International …, 2012 - ieeexplore.ieee.org
In this paper a new method of Petri net array-based synthesis is proposed. The method is
based on the structured encoding of places by means of using minimal numbers of bits …
based on the structured encoding of places by means of using minimal numbers of bits …
Petri nets mapping into reconfigurable logic controllers
The paper concentrates on the behavioral specification of Reconfigurable Logic Controller
programs, given initially as Petri nets and later rewritten in Hardware Description …
programs, given initially as Petri nets and later rewritten in Hardware Description …
Petri net-based specification, analysis and synthesis of logic controllers
The logic control program is usually specified by drawing the Petri net in terms of interface
with the electro-mechanical devices and the environment of the system. In such case it is not …
with the electro-mechanical devices and the environment of the system. In such case it is not …
Hierarchical approach for design of application specific logic controller
In the paper, a structured synthesis method based on hierarchical Petri nets is presented. An
implemented design framework contains the programmable logic synthesis of rule-based …
implemented design framework contains the programmable logic synthesis of rule-based …
An FPGA synthesis of the distributed control systems designed with Petri nets
A Bukowiec, P Mróz - 2012 IEEE 3rd International Conference …, 2012 - ieeexplore.ieee.org
The paper describes a new method for the synthesis of the application specific distributed
control systems, constructed using the FPGA devices. The initial steps of the proposed …
control systems, constructed using the FPGA devices. The initial steps of the proposed …
[PDF][PDF] Synthesis of macro Petri nets into FPGA with distributed memories
A Bukowiec, M Adamski - International Journal of Electronics and …, 2012 - bibliotekanauki.pl
In this paper a new method of Petri net array-based synthesis is proposed. The method is
based on decomposition of colored interpreted macro Petri net into state machine subnets …
based on decomposition of colored interpreted macro Petri net into state machine subnets …
A design framework for FPGA-based dynamically reconfigurable digital controllers
C Paiz, B Kettelhoit, M Porrmann - 2007 IEEE International …, 2007 - ieeexplore.ieee.org
During the past years, it has been shown that dynamic reconfiguration of FPGAs can be
used to enhance the resource efficiency and flexibility of digital controllers. The authors have …
used to enhance the resource efficiency and flexibility of digital controllers. The authors have …
Design of reconfigurable logic controllers from petri net-based specifications
The paper promotes to construct a synthesizable VHDL model from a graphical
representation of Petri Net. The VHDL code provides a clear semantics of graphically …
representation of Petri Net. The VHDL code provides a clear semantics of graphically …
Logic synthesis for FPGAs of interpreted Petri net with common operation memory
A Bukowiec, M Adamski - IFAC Proceedings Volumes, 2012 - Elsevier
The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper.
Proposed method is based on the minimal encoding of places. Places are encoded in …
Proposed method is based on the minimal encoding of places. Places are encoded in …