The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …

When the international technology roadmap of semiconductors (ITRS) started almost five
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …

The interconnect half‐pitch size will reach≈ 20 nm in the coming sub‐5 nm technology
node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be> 4 nm to ensure …

The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay
of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or …

Miniaturization in integrated circuits requires that the Cu diffusion barriers located in
interconnects between the Cu metal line and the dielectric material should scale down …

We investigate the performance and reliability characteristics of Cu interconnects with Ta-
based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the …

To maintain the scaling trends in the complementary metal oxide semiconductor (CMOS)
technology, the thickness of barrier/liner systems used in back-end-of-line (BEOL) …

The Chiplet is widely regarded as the most viable continuation of Moore's Law in the
“Beyond Moore” era. This is primarily due to its capability to circumvent complex process …

Molecular and atomic permeability, thermal stability and interfacial reactions of ultrathin Ta,
TaN and Ta/TaN stack as barrier to Cu/low-k interconnects have been studied. It is shown …

The miniaturization of electronic devices brings severe challenges in the deposition of metal
interconnects in back end of line processing due to a continually decreasing volume …