Twelve years ago, Proceedings of the IEEE devoted a special section to the synchronous
languages. This paper discusses the improvements, difficulties, and successes that have …

Temporal logics are commonly used for reasoning about concurrent systems. Model
checkers and other finite-state verification techniques allow for automated checking of …

One of the main problems in component assembly is how to establish properties on the
assembly code by only assuming a limited knowledge of the single component properties …

Temporal logics are commonly used for reasoning about concurrent systems. Model
checkers and other finite-state verification techniques allow for automated checking of …

Abstract The Synchronous Paradigm proposes an abstract model integrating concurrency
and communication, deterministic thus simple, semantically well-founded thus suitable to …

Verification of present day SoCs is proving to be challenging due to complex interactions
among various subcomponents and IPs, with multiple clock domains and diverse bus …

This paper presents a new model of scenarios, dedicated to the specification and verification
of system behaviours in the context of software product lines (SPL). We draw our inspiration …

Existing notations for expressing time constraints in high-level message sequence charts
(HMSC) may cause ambiguity when used with HMSC compositions such as alternative and …

This workshop is the third one of a series of workshops which objective is to identify the main
lacks of UML for developing real-time embedded systems and the main prospective …