Lockstep dual-core ARM A9: Implementation and resilience analysis under heavy ion-induced soft errors
ÁB de Oliveira, GS Rodrigues… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core
processors against radiation-induced soft errors. The proposed DCLS is applied to an …
processors against radiation-induced soft errors. The proposed DCLS is applied to an …
Radiation testing of a multiprocessor macrosynchronized lockstep architecture with FreeRTOS
Nowadays, high-performance microprocessors are demanded in many fields, including
those with high-reliability requirements. Commercial microprocessors present a good …
those with high-reliability requirements. Commercial microprocessors present a good …
[HTML][HTML] Novel lockstep-based fault mitigation approach for SoCs with roll-back and roll-forward recovery
Abstract All-Programmable System-on-Chips (APSoCs) constitute a compelling option for
employing applications in radiation environments thanks to their high-performance …
employing applications in radiation environments thanks to their high-performance …
A low-overhead reconfigurable RISC-V quad-core processor architecture for fault-tolerant applications
S Shukla, KC Ray - IEEE Access, 2022 - ieeexplore.ieee.org
Radiation can affect the correct behavior of an electronic device. Hence, the
microprocessors used for space missions need to be protected against fault. TMR (Triple …
microprocessors used for space missions need to be protected against fault. TMR (Triple …
Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in FreeRTOS applications
ÁB de Oliveira, GS Rodrigues… - Proceedings of the 30th …, 2017 - dl.acm.org
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a
method for fault-tolerance running on top of FreeRTOS applications. The method was …
method for fault-tolerance running on top of FreeRTOS applications. The method was …
Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a
dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common …
dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common …
Towards a heterogeneous fault-tolerance architecture based on arm and RISC-V processors
Computer systems are permanently present in our daily basis in a wide range of
applications. In systems with mixed-criticality requirements, eg, autonomous driving or …
applications. In systems with mixed-criticality requirements, eg, autonomous driving or …
Run-time recovery mechanism for transient and permanent hardware faults based on distributed, self-organized dynamic partially reconfigurable systems
V Dumitriu, L Kirischian… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Field-Programmable Gate Arrays (FPGAs) are rapidly gaining popularity as implementation
platforms for complex space-borne computing systems. However, such systems are exposed …
platforms for complex space-borne computing systems. However, such systems are exposed …
RapidSmith 2: A framework for BEL-level CAD exploration on Xilinx FPGAs
T Haroldsen, B Nelson, B Hutchings - Proceedings of the 2015 ACM …, 2015 - dl.acm.org
RapidSmith is an open-source framework that allows for the exploration of novel
approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor …
approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor …
Hybrid lockstep technique for soft error mitigation
M Peña-Fernández, A Serrano-Cases… - … on Nuclear Science, 2022 - ieeexplore.ieee.org
This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to
improve the fault tolerance in microprocessors. Our approach takes advantage of modern …
improve the fault tolerance in microprocessors. Our approach takes advantage of modern …