Performance Modeling for FPGAs: Extending the Roofline Model with High‐Level Synthesis Tools
The potential of FPGAs as accelerators for high‐performance computing applications is very
large, but many factors are involved in their performance. The design for FPGAs and the …
large, but many factors are involved in their performance. The design for FPGAs and the …
A generic VHDL template for 2D stencil code applications on FPGAs
M Schmidt, M Reichenbach… - 2012 IEEE 15th …, 2012 - ieeexplore.ieee.org
The efficient realization of self-organizing systems based on 2D stencil code applications,
like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive …
like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive …
Faupu-a design framework for the development of programmable image processing architectures
M Reichenbach, T Lieske, S Vaas… - 2015 International …, 2015 - ieeexplore.ieee.org
The development of fast image processing architectures in smart camera systems is a very
important task. Nowadays, many applications, such as robot control or advanced driver …
important task. Nowadays, many applications, such as robot control or advanced driver …
Performance and resource modeling for FPGAs using high-level synthesis tools
High-performance computing with FPGAs is gaining momentum with the advent of
sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by …
sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by …
[图书][B] Parallel Embedded Computing Architectures
M Schmidt, D Fey, M Reichenbach - 2012 - books.google.com
It was around the years 2003 to 2005 that a dramatic change seized the semiconductor
industry and the manufactures of processors. The increasing of computing performance in …
industry and the manufactures of processors. The increasing of computing performance in …
[PDF][PDF] A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs: ERSA'12 Distinguished Paper
F Richter, M Schmidt, D Fey - Proceedings of the International …, 2012 - world-comp.org
2D and 3D stencil code applications are very common in scientific computing, but their
performance is mostly limited by the memory bandwidth. Elaborate onchip buffering …
performance is mostly limited by the memory bandwidth. Elaborate onchip buffering …
Framework for parameter analysis of FPGA-based image processing architectures
M Reichenbach, B Pfundt, D Fey - … International Conference on …, 2015 - ieeexplore.ieee.org
Image processing algorithms which only work on a local neighbourhood are nearly used in
every image processing application. Very often several iterations are performed on a fixed …
every image processing application. Very often several iterations are performed on a fixed …
Acceleration of streaming applications on FPGAs: architectures, performance strategies and models
B da Silva Gomes - 2019 - biblio.ugent.be
Field-Programmable Gate Arrays (FPGAs) increasingly assume roles as hardware
accelerators which significantly speed up computations in a wide range of streaming …
accelerators which significantly speed up computations in a wide range of streaming …
Area-Efficient Splitting Mechanism for 2D Convolution on FPGA
Real-time image processing in the field of computer vision is not only a challenging task, but
requires several embedded computing considerations. In the present era, FPGA-based …
requires several embedded computing considerations. In the present era, FPGA-based …
[PDF][PDF] Research Article Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools
The potential of FPGAs as accelerators for high-performance computing applications is very
large, but many factors are involved in their performance. The design for FPGAs and the …
large, but many factors are involved in their performance. The design for FPGAs and the …