Interconnect spacing is getting increasingly smaller in advanced technology nodes, which
adversely increases the capacitive coupling of adjacent interconnect wires. It makes …

Deep submicron effects, along with increasing interconnect densities, have increased the
complexity of the routing problem. Whereas previously we could focus on minimizing …

Noise arising from line-to-line coupling is a major problem for deep submicron design, and
present technology trends are causing an increase in this type of noise. Common current …

Routing is one of the most complex stages in the back-end design process. Simple routing
algorithms based on two stages of global routing and detailed routing do not offer …

Presents a novel gridless detailed routing approach based on multilevel optimization. The
multilevel framework with recursive coarsening and refinement in a" V-shaped" flow allows …

Noise, as well as area, delay, and power, is one of the most important concerns in the
design of deep submicrometer integrated circuits. Currently existing algorithms do not …

In this paper we survey major problems faced by EDA tools in tackling deep submicron
(DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay …

As the CMOS technology enters the deep submicron design era, the lateral inter-wire
coupling capacitance becomes the dominant part of load capacitance and makes RC delay …

The migration to using ultra deep submicron (UDSM) process, 0.25 μm or below,
necessitates new design methodologies and EDA tools to address the new design …

As the CMOS technology scaled down to deep sub-micron level, the crosstalk effects due to
the coupling capacitance between interconnection lines has become one of the main …