A survey of techniques for dynamic branch prediction

S Mittal - Concurrency and Computation: Practice and …, 2019 - Wiley Online Library
Branch predictor (BP) is an essential component in modern processors since high BP
accuracy can improve performance and reduce energy by decreasing the number of …

[图书][B] Computer architecture: a quantitative approach

JL Hennessy, DA Patterson - 2011 - books.google.com
Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that
software and technology in the cloud are accessed by digital media, such as cell phones …

Pythia: A customizable hardware prefetching framework using online reinforcement learning

R Bera, K Kanellopoulos, A Nori, T Shahroodi… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

Language acquisition as rational contingency learning

NC Ellis - Applied linguistics, 2006 - academic.oup.com
This paper considers how fluent language users are rational in their language processing,
their unconscious language representation systems optimally prepared for comprehension …

Transient-Execution Attacks: A Computer Architect Perspective

L Fiolhais, L Sousa - ACM Computing Surveys, 2023 - dl.acm.org
Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

Driving cache replacement with {ML-based}{LeCaR}

G Vietri, LV Rodriguez, WA Martinez, S Lyons… - 10th USENIX Workshop …, 2018 - usenix.org
Can machine learning (ML) be used to improve on existing cache replacement strategies?
We propose a general framework called LeCaR that uses the ML technique of regret …

A case for (partially) tagged geometric history length branch prediction

A Seznec, P Michaud - The Journal of Instruction-Level Parallelism, 2006 - inria.hal.science
It is now widely admitted that in order to provide state-of-the-art accuracy, a conditional
branch predictor must combine several predictions. Recent research has shown that an …

Construction and use of linear regression models for processor performance analysis

PJ Joseph, K Vaswani… - The Twelfth International …, 2006 - ieeexplore.ieee.org
Processor architects have a challenging task of evaluating a large design space consisting
of several interacting parameters and optimizations. In order to assist architects in making …

Fast path-based neural branch prediction

DA Jiménez - … . 36th Annual IEEE/ACM International Symposium …, 2003 - ieeexplore.ieee.org
Microarchitectural prediction based on neural learning has received increasing attention in
recent years. However, neural prediction remains impractical because its superior accuracy …

Hermes: Accelerating long-latency load requests via perceptron-based off-chip load prediction

R Bera, K Kanellopoulos… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Long-latency load requests continue to limit the performance of modern high-performance
processors. To increase the latency tolerance of a processor, architects have primarily relied …