Low-power high-throughput LDPC decoder using non-refresh embedded DRAM

YS Park, D Blaauw, D Sylvester… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
The majority of the power consumption of a high-throughput LDPC decoder is spent on
memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is …

Architectures for cognitive radio testbeds and demonstrators—an overview

O Gustafsson, K Amiri, D Andersson… - 2010 Proceedings of …, 2010 - ieeexplore.ieee.org
Wireless communication standards are developed at an ever-increasing rate of pace, and
significant amounts of effort is put into research for new communication methods and …

ASIP for 5G and Beyond: Opportunities and Vision

S Shahabuddin, A Mämmelä, M Juntti… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The tutorial discusses application-specific instruction-set processors (ASIP) and their
potential for the fifth generation (5G) and beyond 5G networks. ASIP is a class of customized …

A unified forward error correction accelerator for multi-mode Turbo, LDPC, and polar decoding

Y Yue, T Ajayi, X Liu, P Xing, Z Wang… - Proceedings of the …, 2022 - dl.acm.org
Forward error correction (FEC) is a critical component in communication systems as the
errors induced by noisy channels can be corrected using the redundancy in the coded …

Implementation trade-offs of soft-input soft-output MAP decoders for convolutional codes

C Studer, S Fateh, C Benkeser… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Soft-input soft-output (SISO) maximum a-posteriori (MAP) decoders for convolutional codes
(CCs) are an integral part of many modern wireless communication systems. Specifically …

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates

M Winter, S Kunze, EP Adeva… - … Solid-State Circuits …, 2012 - ieeexplore.ieee.org
In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTE-Advanced,
receiver terminals have to support numerous operating modes for each protocol [1], as well …

Multicore type error correction processing system and error correction processing apparatus

T Kobori, S Kunze, E Matus, G Fettweis - US Patent 9,250,996, 2016 - Google Patents
In a multicore type error correction processing system which can simultaneously cope with a
plurality of error correction methods and a plurality of code lengths, an interconnect part 11 …

2PARMA: parallel paradigms and run-time management techniques for many-core architectures

C Silvano, W Fornaciari, SC Reghizzi, G Agosta… - VLSI 2010 Annual …, 2011 - Springer
The 2PARMA project focuses on the development of parallel programming models and run-
time resource management techniques to exploit the features of many-core processor …

Investigation of turbo decoding techniques based on lottery arbiter in 3D network on chip

M Suaganthy, A Karthikeyan, PG Kuppusamy - Microprocessors and …, 2019 - Elsevier
In this digital age, turbo Codes have been largely favoured in various high speed wireless
communication systems standards (3GPP-LTE, WiMAX and WiFi). These codes are …

A multi-threaded coarse-grained array processor for wireless baseband

T Vander Aa, M Palkovic, M Hartmann… - 2011 IEEE 9th …, 2011 - ieeexplore.ieee.org
Throughput of wireless communication standards ever increases. Computation
requirements for systems implementing those standards increase even more. On battery …