This paper presents a wake-up & shut-down ring oscillator based Random Number
Generator (RNG) together with a new method of duty cycle correction circuit for …

(Continued) Primary Examiner—Adam Houston (74) Attorney, Agent, or Firm—Fenwick &
West LLP (57) ABSTRACT A duty cycle correction (DCC) circuit includes first and second …

A low power method of clock signal duty cycle adjustment is presented in this paper. The
proposed architecture produces a synchronous signal in the output of system with 50±1 …

A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To
neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of …

A method of serial links output data and clock signals setup and hold times correction
presented in this paper. The proposed architecture produces corrected clock which have …

This paper introduces the implementation of a monolithic random number generator. For that
purpose, dual oscillator architecture with an irregular sampling of a regular signal is …

A method of serializer and deserializer output data signals duty cycle correction is presented
in this paper. The proposed architecture produces a data signal in the output of …

A fast-locking, high-precision, and low-jitter pulsewidth control loop (PWCL) for high-speed
high-resolution analog-to-digital converter is presented. Only through controlling the delay of …

Differential clock cross point correction method is presented in this paper. The proposed
method provides differential clock with minimum crossing error over PVT, which is needed to …

A clock signal conversion circuit includes an amplification circuit configured to amplify a
differential clock signal having sub rail-to-rail voltage swings relative to a supply voltage …