Survey of scheduling techniques for addressing shared resources in multicore processors

S Zhuravlev, JC Saez, S Blagodurov… - ACM Computing …, 2012 - dl.acm.org
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for
modern computing platforms and will most likely continue to be dominant well into the …

Tpp: Transparent page placement for cxl-enabled tiered-memory

HA Maruf, H Wang, A Dhanotia, J Weiner… - Proceedings of the 28th …, 2023 - dl.acm.org
The increasing demand for memory in hyperscale applications has led to memory becoming
a large portion of the overall datacenter spend. The emergence of coherent interfaces like …

Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory

P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu… - ACM SIGARCH …, 2016 - dl.acm.org
Processing-in-memory (PIM) is a promising solution to address the" memory wall"
challenges for future computer systems. Prior proposed PIM architectures put additional …

TMO: Transparent memory offloading in datacenters

J Weiner, N Agarwal, D Schatzberg, L Yang… - Proceedings of the 27th …, 2022 - dl.acm.org
The unrelenting growth of the memory needs of emerging datacenter applications, along
with ever increasing cost and volatility of DRAM prices, has led to DRAM being a major …

Thermostat: Application-transparent page management for two-tiered main memory

N Agarwal, TF Wenisch - Proceedings of the Twenty-Second …, 2017 - dl.acm.org
The advent of new memory technologies that are denser and cheaper than commodity
DRAM has renewed interest in two-tiered main memory schemes. Infrequently accessed …

Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches

MK Qureshi, YN Patt - 2006 39th Annual IEEE/ACM …, 2006 - ieeexplore.ieee.org
This paper investigates the problem of partitioning a shared cache between multiple
concurrently executing applications. The commonly used LRU policy implicitly partitions a …

Software-defined far memory in warehouse-scale computers

A Lagar-Cavilla, J Ahn, S Souhlal, N Agarwal… - Proceedings of the …, 2019 - dl.acm.org
Increasing memory demand and slowdown in technology scaling pose important challenges
to total cost of ownership (TCO) of warehouse-scale computers (WSCs). One promising idea …

A survey of architectural techniques for DRAM power management

S Mittal - … Journal of High Performance Systems Architecture, 2012 - inderscienceonline.com
Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been estimated …

Towards practical page coloring-based multicore cache management

X Zhang, S Dwarkadas, K Shen - Proceedings of the 4th ACM European …, 2009 - dl.acm.org
Modern multi-core processors present new resource management challenges due to the
subtle interactions of simultaneously executing processes sharing on-chip resources …

Efficient {MRC} construction with {SHARDS}

CA Waldspurger, N Park, A Garthwaite… - 13th USENIX Conference …, 2015 - usenix.org
Reuse-distance analysis is a powerful technique for characterizing temporal locality of
workloads, often visualized with miss ratio curves (MRCs). Unfortunately, even the most …