Generation of an error set that emulates software faults based on field data
J Christmansson, R Chillarege - Proceedings of Annual …, 1996 - ieeexplore.ieee.org
A significant issue in fault injection experiments is that the injected faults are representative
of software faults observed in the field. Another important issue is the time used, as we want …
of software faults observed in the field. Another important issue is the time used, as we want …
Efficient dynamic virtual channel organization and architecture for NoC systems
M Oveis-Gharan, GN Khan - IEEE Transactions on Very Large …, 2015 - ieeexplore.ieee.org
A growing number of processing cores on a chip require an efficient and scalable
communication structure such as network on chip (NoC). The channel buffer organization of …
communication structure such as network on chip (NoC). The channel buffer organization of …
Latency improvement by using fill VC allocation for network on chip
Abstract Network on Chip (NoC) is gaining popularity as an interconnect structure for
complex multicore system on chip. The overall performance of NoC can be enhanced by …
complex multicore system on chip. The overall performance of NoC can be enhanced by …
Network-on-chip router design with buffer-stealing
WT Su, JS Shen, PA Hsiung - 16th Asia and South Pacific …, 2011 - ieeexplore.ieee.org
Communication in a Network-on-Chip (NoC) can be made more efficient by designing faster
routers, using larger buffers, larger number of ports and channels, and adaptive routing, all …
routers, using larger buffers, larger number of ports and channels, and adaptive routing, all …
一种适于片上路由器的自适应缓冲调整策略
石伟， 郭御风， 窦强， 张明， 任巨 - 国防科技大学学报, 2013 - journal.nudt.edu.cn
在典型的片上网络路由节点中, 来自不同方向的报文被存储在相互独立的缓冲资源中.
在网络负载不均衡的情况下, 某些方向的报文将很快填满该方向的缓冲, 而其他方向仍可能有较 …
在网络负载不均衡的情况下, 某些方向的报文将很快填满该方向的缓冲, 而其他方向仍可能有较 …
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer
W Shi, W Xu, H Ren, Q Dou, Z Wang… - 2011 IEEE 29th …, 2011 - ieeexplore.ieee.org
Buffer resources are key components of the on-chip router, shared-buffer structures are
proposed to improve performance and reduce power consumption. This paper presents a …
proposed to improve performance and reduce power consumption. This paper presents a …
Benefits of selective packet discard in networks-on-chip
A Lankes, T Wild, S Wallentowitz… - ACM Transactions on …, 2012 - dl.acm.org
Today, Network on Chip concepts principally assume inherent lossless operation.
Considering that future nanometer CMOS technologies will witness increased sensitivity to …
Considering that future nanometer CMOS technologies will witness increased sensitivity to …
Flexvc: Flexible virtual channel management in low-diameter networks
Deadlock avoidance mechanisms for lossless lowdistance networks typically increase the
order of virtual channel (VC) index with each hop. This restricts the number of buffer …
order of virtual channel (VC) index with each hop. This restricts the number of buffer …
DAMQ-based schemes for efficiently using the buffer spaces of a NoC router
MAJ Jamali, A Khademzadeh - arXiv preprint arXiv:0910.1852, 2009 - arxiv.org
In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer
schemes for fault tolerance systems on chip applications that require an interconnection …
schemes for fault tolerance systems on chip applications that require an interconnection …
Two-level FIFO buffer design for routers in on-chip interconnection networks
The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip
(SoC) designs. The buffer architecture and size, however, dominate the performance of …
(SoC) designs. The buffer architecture and size, however, dominate the performance of …