Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
Nanoelectromechanical switches for low-power digital computing
A Peschot, C Qian, TJ King Liu - Micromachines, 2015 - mdpi.com
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-
semiconductor (CMOS) transistors has become a major concern as the power consumption …
semiconductor (CMOS) transistors has become a major concern as the power consumption …
Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET
UK Das, TK Bhattacharyya - IEEE transactions on electron …, 2020 - ieeexplore.ieee.org
The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped
FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To …
FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To …
BSIM—SPICE models enable FinFET and UTB IC designs
Two turn-key surface potential-based compact models are developed to simulate multigate
transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is …
transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is …
Body dust: Well beyond wearable and implantable sensors
S Carrara - IEEE Sensors Journal, 2020 - ieeexplore.ieee.org
Over the last 20 years, the field of Smart Dust has been proposed and demonstrated. Almost
in the same period, implantable and wearable sensors for human monitoring have been …
in the same period, implantable and wearable sensors for human monitoring have been …
Comprehensive and accurate parasitic capacitance models for two-and three-dimensional CMOS device structures
J Lacord, G Ghibaudo, F Boeuf - IEEE Transactions on Electron …, 2012 - ieeexplore.ieee.org
In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly
parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar …
parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar …
High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
Wafer-scale defect-free planar III–V nanowire (NW) arrays with∼ 100% yield and precisely
defined positions are realized via a patterned vapor–liquid–solid (VLS) growth method …
defined positions are realized via a patterned vapor–liquid–solid (VLS) growth method …
[图书][B] Compact models for integrated circuit design: conventional transistors and beyond
SK Saha - 2015 - library.oapen.org
This modern treatise on compact models for circuit computer-aided design (CAD) presents
industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor …
industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor …
Review on analog/radio frequency performance of advanced silicon MOSFETs
V Passi, JP Raskin - Semiconductor Science and Technology, 2017 - iopscience.iop.org
Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor
(MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This …
(MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This …
Design guidelines for sub-12 nm nanowire MOSFETs
M Salmani-Jelodar, SR Mehrotra… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Traditional thinking assumes that a light effective mass (m*), high mobility material will result
in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field …
in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field …