In accordance with some embodiments, a system and method for designing a circuit device
is disclosed. In the method, a block of circuitry in the circuit device is identified. An initial …

A UNIFIED MODEL OF PATTERN-MATCHING CIRCUITS FOR FIELD-PROGRAMMABLE GATE
ARRAYS Page 1 A UNIFIED MODEL OF PATTERN-MATCHING CIRCUITS FOR …

With the recent advances in hardware technologies like advanced CPUs and GPUs and the
large availability of open-source libraries, machine learning has penetrated various …

Design closure in general VLSI physical design flows and FPGA physical design flows is an
important and time-consuming problem. Routing itself can consume as much as 70% of the …

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both
hardware-level performance and post-fabrication flexibility. However, any one architecture is …

This paper presents an analytical model that relates FPGA architectural parameters to the
logic size and depth of an FPGA implementation. In particular, the model relates the lookup …

A priori wirelength estimation is concerned with predicting various wirelength characteristics
before placement. In this work we propose a novel, accurate estimator of net lengths. We …

This paper describes an analytical model that relates the architectural parameters of an
FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous …

We propose a neural network based approach for estimating the total wirelength of a digital
circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural …

Interconnect planning is becoming an important design issue for large field programmable
gate array (FPGA)-based designs. One of the most important issues for planning …