A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

C Sun, W Liu, J Cheng, N Sun, Z Peng… - … Journal of Circuit …, 2023 - Wiley Online Library
In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is
designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of …

RC4-AccSuite: A hardware acceleration suite for RC4-like stream ciphers

A Khalid, G Paul… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
We present RC4-AccSuite, a hardware accelerator, which combines the flexibility of an
application specific instruction set processor and the performance of an application specific …

A novel symmetric cryptography algorithm for fast and secure encryption

A Achuthshankar… - 2015 IEEE 9th International …, 2015 - ieeexplore.ieee.org
Data encryption is the best way to provide secure communication. Even though a lot of
encryption schemes are available, this paper proposes a simple, fast and secure encryption …

Quad-RC4: merging four RC4 states towards a 32-bit stream cipher

G Paul, S Maitra, A Chattopadhyay - Cryptology ePrint Archive, 2013 - eprint.iacr.org
RC4 has remained the most popular software stream cipher since the last two decades. In
parallel to cryptanalytic attempts, researchers have come up with many variants of RC4 …

Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4

A Chattopadhyay, G Paul - … Conference on VLSI and System-on …, 2012 - ieeexplore.ieee.org
Ubiquitous information exchange and processing require low cost and secure cryptographic
primitives. RC4 is one of the most popular stream ciphers with well-known strengths and …

One word/cycle HC-128 accelerator via state-splitting optimization

A Khalid, P Ravi, A Chattopadhyay, G Paul - Progress in Cryptology …, 2014 - Springer
As today's high performance embedded systems are heterogeneous platforms, a crisp
boundary between the software and the hardware ciphers is fast getting murky. This work …

[图书][B] Domain Specific High-Level Synthesis for Cryptographic Workloads

A Khalid, G Paul, A Chattopadhyay - 2019 - Springer
This era is witnessing a phenomenal increase in the amount and frequency of the
information exchange. The imminent Internet of Things paradigm underpins an network of …

Three snakes in one hole: the first systematic hardware accelerator design for sosemanuk with optional serpent and snow 2.0 modes

G Paul, A Chattopadhyay - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
With increasing usage of hardware accelerators in modern heterogeneous System-on-Chips
(SoCs), the distinction between hardware and software is no longer rigid. The domain of …

[PDF][PDF] Three Snakes in One Hole: A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.

G Paul, A Chattopadhyay - IACR Cryptol. ePrint Arch., 2013 - Citeseer
With increasing usage of hardware accelerators in modern heterogeneous Systemon-Chips
(SoCs), the distinction between hardware and software is no longer rigid. The domain of …

Implementation of reversible Data Hiding in Encrypted Image using AS Algorithm

A Achuthshankar, A Achuthshankar… - … on Green Computing …, 2015 - ieeexplore.ieee.org
Data encryption is the best way to provide secure communication. The paper presents a
novel approach to data hiding using a symmetric stream cipher known as AS Algorithm …