Advances in IC fabrication technology, coupled with aggressive circuit design, have led to
exponential growth of IC speed and integration levels. For these improvements to benefit …

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case
phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS …

This paper describes a new high-density low-power circuit approach for implementing static
random access memory (SRAM) using low current density resonant tunneling diodes …

Apparatus and methods are disclosed for adjusting phase of data signals to compensate for
phase-offset variations between devices during normal operation. The phase of data signals …

A high speed CMOS signaling interface for application in multiprocessor interconnection
networks has been developed. The interface utilizes IV push-pull drivers, a delay line phase …

The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the
performance of digital systems. In intra-system interfaces where both latency and bandwidth …

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in
a 0.8-/spl mu/m CMOS process. An experimental receiving front-end circuit demonstrates the …

There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …

This paper describes voltage and timing margins and design trade-offs in low-cost parallel
links. Results from a transceiver prototype demonstrate that per-pin skew compensation …

This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data
communication. The CMOS serial link is a robust and low-cost solution to high data rate …