Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
A 320-fs RMS jitter and–75-dBc reference-spur ring-DCO-based digital PLL using an optimal-threshold TDC
This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital
phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In …
phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In …
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114
An ultra-low-jitter, ring-LC-hybrid injection-locked clock multiplier (ILCM) is presented to
achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type …
achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type …