An embedded system-on-chip architecture for real-time visual detection and matching
Detecting and matching image features is a fundamental task in video analytics and
computer vision systems. It establishes the correspondences between two images taken at …
computer vision systems. It establishes the correspondences between two images taken at …
A real-time embedded architecture for SIFT
SIFT has shown a great success in various computer vision applications. However, its large
computational complexity has been a challenge to most embedded implementations. This …
computational complexity has been a challenge to most embedded implementations. This …
Fully pipelined FPGA-based architecture for real-time SIFT extraction
Image feature extraction constitutes a fundamental task in robotic vision applications. Scale-
Invariant Feature Transform (SIFT) has been widely used as a robust method for detecting …
Invariant Feature Transform (SIFT) has been widely used as a robust method for detecting …
Multiplier-less stream processor for 2D filtering in visual search applications
GD Licciardo, C Cappetta… - … on Circuits and …, 2016 - ieeexplore.ieee.org
A new 2D convolution-based filter is presented, which is specifically designed to improve
visual search applications. It exploits a new radix-3 partitioning method of integer numbers …
visual search applications. It exploits a new radix-3 partitioning method of integer numbers …
FPGA-based hardware design for scale-invariant feature transform
SA Li, WY Wang, WZ Pan, CCJ Hsu, CK Lu - IEEE Access, 2018 - ieeexplore.ieee.org
This paper proposes a novel hardware design method of scale-invariant feature transform
(SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the …
(SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the …
FPGA optimization of convolution-based 2D filtering processor for image processing
GD Licciardo, C Cappetta… - 2016 8th Computer …, 2016 - ieeexplore.ieee.org
The Bachet weight decomposition method is used to design a new 2D convolution-based
filter, specifically aimed to image processing. The filter substitutes multipliers with simplified …
filter, specifically aimed to image processing. The filter substitutes multipliers with simplified …
Hardware coprocessor for stripe-based interest point detection
M Vigliar, GD Licciardo - US Patent 9,020,276, 2015 - Google Patents
A hardware coprocessor architecture calculates the Differ ence-of-Gaussian (DoG) pyramid
of an input image and extracts from this the interest points to be used in several image …
of an input image and extracts from this the interest points to be used in several image …
Frame buffer-less stream processor for accurate real-time interest point detection
A high performance HW accelerator is proposed to extract and refine the Interest Points from
images, by accurately calculating the Difference-of-Gaussian and using refinement …
images, by accurately calculating the Difference-of-Gaussian and using refinement …
Domain-Specific Optimisations for Image Processing on FPGAs
Image processing algorithms on FPGAs have increasingly become more pervasive in real-
time vision applications. Such algorithms are computationally complex and memory …
time vision applications. Such algorithms are computationally complex and memory …
Design and implementation of low-power hardware architecture with single-cycle divider for on-line clustering algorithm
A dual-stage hardware architecture that supports two kinds of moving averages for the on-
line clustering algorithm is proposed. The architectural design of this work is different from …
line clustering algorithm is proposed. The architectural design of this work is different from …