[图书][B] Reconfigurable computing: the theory and practice of FPGA-based computation
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …
between the separate worlds of hardware and software design—the key feature of …
[图书][B] Reconfigurable computing: Accelerating computation with field-programmable gate arrays
MB Gokhale, PS Graham - 2006 - books.google.com
A one-of-a-kind survey of the field of Reconfigurable Computing Gives a comprehensive
introduction to a discipline that offers a 10X-100X acceleration of algorithms over …
introduction to a discipline that offers a 10X-100X acceleration of algorithms over …
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete
SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an …
SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an …
Towards simulator-like observability for FPGAs: A virtual overlay network for trace-buffers
E Hung, SJE Wilton - Proceedings of the ACM/SIGDA international …, 2013 - dl.acm.org
The rising complexity of verification has led to an increase in the use of FPGA prototyping,
which can run at significantly higher operating frequencies and achieve much higher …
which can run at significantly higher operating frequencies and achieve much higher …
Generating efficient context-switch capable circuits through autonomous design flow
Commercial off-the-shelf (COTS) Field-Programmable Gate Arrays (FPGAs) are becoming
increasingly powerful. In addition to their huge hardware resources, they are also integrated …
increasingly powerful. In addition to their huge hardware resources, they are also integrated …
Incremental trace-buffer insertion for FPGA debug
E Hung, SJE Wilton - IEEE Transactions on Very Large Scale …, 2013 - ieeexplore.ieee.org
As integrated circuits encapsulate more functionality and complexity, verifying that these
devices operate correctly under all scenarios is an increasingly difficult task. Rather than …
devices operate correctly under all scenarios is an increasingly difficult task. Rather than …
Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs
A Tiwari, KA Tomko - Proceedings of the 2003 Asia and South Pacific …, 2003 - dl.acm.org
This paper describes a structured and area efficient approach for in-situ debugging of
application for FPGA based reconfigurable systems. A scan chain is inserted into the …
application for FPGA based reconfigurable systems. A scan chain is inserted into the …
Live migration for OpenCL FPGA accelerators
FPGAs are currently being deployed at a large scale across data-centres for various
applications because of their performance and power benefits. In particular, cloud service …
applications because of their performance and power benefits. In particular, cloud service …
Enabling low impact, rapid debug for highly utilized FPGA designs
R Hale, B Hutchings - 2018 28th International Conference on …, 2018 - ieeexplore.ieee.org
Inserting soft logic analyzers into FPGA circuits is a common way to provide signal visibility
at run-time, helping users locate bugs in their designs. However, this can become infeasible …
at run-time, helping users locate bugs in their designs. However, this can become infeasible …
Debugging support for pattern-matching languages and accelerators
Programs written for hardware accelerators can often be difficult to debug. Without adequate
tool support, program maintenance tasks such as fault localization and debugging can be …
tool support, program maintenance tasks such as fault localization and debugging can be …