A 4 GHz 60 dB variable gain amplifier with tunable DC offset cancellation in 65 nm CMOS

TB Kumar, K Ma, KS Yeo - IEEE Microwave and Wireless …, 2014 - ieeexplore.ieee.org
This letter presents a compact CMOS based variable gain amplifier with 60 dB gain control
range and a feedback reconfigurable dc offset cancellation. The design is a four-stage fully …

A Low-Power Interference-Tolerance Wideband Receiver for 802.11af/ah Long-Range Wi-Fi With Post-LNA Active -Path Filter

HN Nguyen, KS Kim, SH Han, JY Lee… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
A low-power interference-tolerance wideband receiver with post-LNA active N-path filter for
RF channel selection is proposed for 802.1 af/ah long-range Wi-Fi standards. By leveraging …

Designing a Ring‐VCO for RFID Transponders in 0.18 μm CMOS Process

J Jalil, MBI Reaz, MAS Bhuiyan… - The Scientific World …, 2014 - Wiley Online Library
In radio frequency identification (RFID) systems, performance degradation of phase locked
loops (PLLs) mainly occurs due to high phase noise of voltage‐controlled oscillators …

A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11 b/Bluetooth receiver

B Xia, A Valdes-Garcia… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
This work presents a configurable time-interleaved pipeline architecture as an efficient
solution for the ADC design in high data rate multi-standard radios. The ADC is implemented …

A CMOS highly linear digitally programmable active-RC design approach

HA Alzaher - IEEE Transactions on Circuits and Systems I …, 2011 - ieeexplore.ieee.org
A new approach providing the active-RC integrator with programmable time constant is
proposed. An inherently linear current division network (CDN) preserving the high linearity …

A 5-Gb/s 66 dB CMOS variable-gain amplifier with reconfigurable DC-offset cancellation for multi-standard applications

Z Liu, Y Wu, C Zhao, J Benedikt, K Kang - IEEE Access, 2018 - ieeexplore.ieee.org
This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset
cancellation (DCOC) for multi-standard applications. In this design, a cell-based design …

A VHDL-AMS simulation environment for an UWB impulse radio transceiver

MR Casu, M Crepaldi… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Ultrawideband (UWB) communication based on the impulse radio paradigm is becoming
increasingly popular. According to the IEEE 802.15 WPAN low rate alternative PHY Task …

Spur reduction architecture for multiphase fractional PLLs

D Biswas, TK Bhattacharyya - IET Circuits, Devices & Systems, 2019 - Wiley Online Library
In this study, a multiphase fractional phase‐locked loop (PLL) is presented with methods to
reduce spurs. General causes of spurs are non‐idealities of the phase‐frequency detector …

A 2.4 GHz ISM-band highly digitized receiver based on a variable gain LNA and a subsampled ADC

D Haghighitalab, D Belfort, A Kiliç… - … Integrated Circuits and …, 2018 - Springer
In this paper, we present a complete multi-standard receiver based on a variable-gain LNA
and an RF subsampled Sigma-Delta ADC. The receiver includes an RF digital down …

Causes of PLL spurs and their modeling

D Biswas, TK Bhattacharyya - Analog Integrated Circuits and Signal …, 2019 - Springer
Spurs are generated at the output of conventional PLLs due to nonidealities of the phase-
frequency detector and charge pump, and variation in the modulus of the frequency divider …